Performance-aware Scheduling of Multicore Time-critical Systems
2016 (English)In: / [ed] IEEE, IEEE, 2016, 105-114 p.Conference paper (Refereed)
Despite attractiveness of multicore processors for embedded systems, the potential performance gains need to be studied in the context of real-time task scheduling and memory interference. This paper explores performance-aware schedula-bility of multicore systems by evaluating the performance when changing scheduling policies (as design parameters). The modelbased framework we build enables analyzing the performance of multicore time-critical systems using processor-centric and memory-centric scheduling policies. The system architecture we consider consists of a set of cores with a local cache and sharing the cache level L2 and main memory (DRAM). The metrics we use to compare the performance achieved by different configurations of a system are: 1) utilization of the cores; and 2) the maximum delay per access request to shared cache and DRAM. Our framework, realized using UPPAAL, can be viewed as an engineering tool to be used during design stages to identify the scheduling policies that provide better performance for a given system while maintaining system schedulability. As a proof of concept, we analyze and compare 2 different cases studies.
Place, publisher, year, edition, pages
IEEE, 2016. 105-114 p.
IdentifiersURN: urn:nbn:se:liu:diva-134019DOI: 10.1109/MEMCOD.2016.7797753ISI: 000392220600014ISBN: 978-1-5090-2791-0 (print)OAI: oai:DiVA.org:liu-134019DiVA: diva2:1066409
14th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)
Funding agencies: Swedish Governmental Agency for Innovation Systems [NFFP6-2014-00917] 2017-01-182017-01-182017-02-20