Design of a VCO-based ADC in 28 nm CMOS
2016 (English)In: 2016 2ND IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS), IEEE , 2016Conference paper (Refereed)
A VCO-based ADC is designed and synthesized in a 28 nm FDSOI CMOS process to investigate the scaling benefits of all-digital analog-to-digital conversion. A coarse-fine quantizer is used to obtain high energy efficiency. Common patterns of sample errors at the multi-phase VCO output are identified and mitigated. Final design indicates an ENOB of 13.4 and a Walden FoM of 4.3 fJ/step over a 5 MHz bandwidth while sampling at 150 MHz, according to schematic simulation of the synthesized netlist.
Place, publisher, year, edition, pages
IEEE , 2016.
IdentifiersURN: urn:nbn:se:liu:diva-134514DOI: 10.1109/NORCHIP.2016.7792914ISI: 000391620400041ISBN: 978-1-5090-1095-0 OAI: oai:DiVA.org:liu-134514DiVA: diva2:1074342
2nd IEEE Nordic Circuits and Systems Conference (NORCAS)