Asynchronous Clock Generator for a 14-bit Two-stage Pipelined SAR ADC in 0.18 mu m CMOS
2016 (English)In: 2016 2ND IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS), IEEE , 2016Conference paper (Refereed)
This paper describes the design and implementation of an asynchronous clock generator which has been used in a 14-bit two-stage pipelined SAR ADCs for low-power sensor applications. A self-synchronization loop based on an edge detector was utilized to generate an internal clock with variable phase and frequency. A tunable delay element enables to allocate the available time for the switch capacitor DACs and the gain-stage. Thereafter, three separate asynchronous clock generators were implemented to create the control signals for two sub-ADCs and the gain-stage between. Finally, a 14-bit asynchronous two-stage pipelined SAR ADC was designed and simulated in 0.18 mu m CMOS. Detailed pre-layout circuit simulations show that the ADC achieves a SNDR of 83.5 dB while consuming 2.13 mu W with a sampling rate of 10 kS/s. The corresponding FoM is 177.2 dB.
Place, publisher, year, edition, pages
IEEE , 2016.
Asynchronous clock generator; pipelined SAR ADC; self-synchronization; low-power sensors; delay element
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-134513DOI: 10.1109/NORCHIP.2016.7792910ISI: 000391620400037ISBN: 978-1-5090-1095-0 OAI: oai:DiVA.org:liu-134513DiVA: diva2:1074345
2nd IEEE Nordic Circuits and Systems Conference (NORCAS)