liu.seSearch for publications in DiVA
Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Mitigation of Sampling Errors in VCO-Based ADCs
Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
2017 (English)In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 64, no 7, 1730-1739 p.Article in journal (Refereed) Published
Abstract [en]

Voltage-controlled-oscillator-based analog-to-digital converter (ADC) is a scaling-friendly architecture to build ADCs in fine-feature complimentary metal-oxide-semiconductor processes. Lending itself to an implementation with digital components, such a converter enables design automation with existing digital CAD hence reducing design and porting costs compared with a custom design flow. However, robust architectures and circuit techniques that reduce the dependence of performance on component accuracy are required to achieve good performance while designing converters with low accuracy components like standard cells in deeply-scaled processes. This paper investigates errors resulting from the sampling of a fast switching multi-phase ring oscillator output. A scheme employing ones-counters is proposed to encode the sampled ring oscillator code into a binary representation, which is resilient to a class of sampling induced errors modeled by the temporal reordering of the transitions in the ring. In addition to correcting errors caused by deterministic reordering, proposed encoding suppresses conversion errors in the presence of arbitrary reordering patterns that may result from automatic place-and-route in wire-delay dominated processes. The error suppression capability of the encoding is demonstrated using MATLAB simulation. The proposed encoder reduces the error caused by the random reordering of six subsequent bits in the sampled signal from 31 to 2 LSBs for a 31-stage oscillator.

Place, publisher, year, edition, pages
New York: Institute of Electrical and Electronics Engineers (IEEE), 2017. Vol. 64, no 7, 1730-1739 p.
Keyword [en]
Analog-to-digital, VCO-based, ADC, sampling error, time-domain, synthesis, deep submicrometer technology, error correction, encoding, ring oscillator, ones-counter, non-ideal sampling, synthesis, place-and-route, sigma-delta
National Category
Signal Processing Embedded Systems Computer Engineering Telecommunications
Identifiers
URN: urn:nbn:se:liu:diva-137327DOI: 10.1109/TCSI.2017.2670058ISI: 000404294900009OAI: oai:DiVA.org:liu-137327DiVA: diva2:1095228
Available from: 2017-05-12 Created: 2017-05-12 Last updated: 2017-08-07Bibliographically approved
In thesis
1. Design of VCO-based ADCs
Open this publication in new window or tab >>Design of VCO-based ADCs
2016 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Today's complex electronic systems with billions of transistors on a single die are enabled by the aggressive scaling down of the device feature size at an exponential rate as predicted by the Moore's law. Digital circuits benefit from technology scaling to become faster, more energy efficient as well as more area efficient as the feature size is scaled down. Moreover, digital design also benefits from mature CAD tools that simplify the design and cross-technology porting of complex systems, leveraging on a cell-based design methodology. On the other hand, the design of analog circuits is getting increasingly difficult as the feature size scales down into the deep nanometer regime due to a variety of reasons like shrinking voltage headroom, reducing intrinsic gain of the devices, increasing noise coupling between circuit nodes due to shorter distances etc. Furthermore, analog circuits are still largely designed with a full custom design ow that makes their design and porting tedious, slow, and expensive. In this context, it is attractive to consider realizing analog/mixed-signal circuits using standard digital components. This leads to scaling-friendly mixed-signal blocks that can be designed and ported using the existing CAD framework available for digital design. The concept is already being applied to mixed-signal components like frequency synthesizers where all-digital architectures are synthesized using standard cells as basic components. This can be extended to other mixed-signal blocks like digital-to-analog and analog to- digital converters as well, where the latter is of particular interest in this thesis.

A voltage-controlled oscillator (VCO)-based analog-to-digital converter (ADC) is an attractive architecture to achieve all-digital analog-to digital conversion due to favorable properties like shaping of the quantization error, inherent anti-alias filtering etc. Here a VCO operates as a signal integrator as well as a quantizer. A converter employing a ring oscillator as the VCO lends itself to an all-digital implementation.

In this dissertation, we explore the design of VCO-based ADCs synthesized using digital standard cells with the long-term goal of achieving high performance data converters built from low accuracy switch components. In a first step, an ADC is designed using vendor supplied standard cells and fabricated in a 65 nm CMOS process. The converter delivers an 8-bit ENOB over a 25 MHz bandwidth while consuming 3.3 mW of power resulting in an energy efficiency of 235 fJ/step (Walden FoM). Then we utilize standard digital CAD tools to synthesize converter designs that are fully described using a hardware description language. A polynomial-based digital post-processing scheme is proposed to correct for the VCO nonlinearity. In addition, pulse modulation schemes like delta modulation and asynchronous sigma-delta modulation are used as a signal pre-coding scheme, in an attempt to reduce the impact of VCO nonlinearity on converter performance. In order to investigate the scaling benefits of all-digital data conversion, a VCO-based converter is designed in a 28 nm CMOS process. The design delivers a 13.4-bit ENOB over a 5 MHz bandwidth achieving an energy efficiency of 4.3 fJ/step according to post-synthesis schematic simulation, indicating that such converters have the potential of achieving good performance in deeply scaled processes by exploiting scaling benefits. Furthermore, large conversion errors caused by non-ideal sampling of the oscillator phase are studied. An encoding scheme employing ones counters is proposed to code the sampled ring oscillator output into a number, which is resilient to a class of sampling induced errors modeled by temporal reordering of the transitions in the ring. The proposed encoding reduces the largest error caused by random reordering of up to six subsequent bits in the sampled signal from 31 to 2 LSBs. Finally, the impact of process, voltage, and temperature (PVT) variations on the performance while operating the converter from a subthreshold supply is investigated. PVT-adaptive solutions are suggested as a means to achieve energy-efficient operation over a wide range of PVT conditions.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2016. 31 p.
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1812
National Category
Electrical Engineering, Electronic Engineering, Information Engineering Signal Processing Computer Science Telecommunications
Identifiers
urn:nbn:se:liu:diva-132789 (URN)10.3384/diss.diva-1049563 (DOI)9789176856246 (ISBN)
Public defence
2016-12-16, Transformen, B-huset, Campus Valla, Linköping, 10:15 (English)
Opponent
Supervisors
Available from: 2016-11-25 Created: 2016-11-25 Last updated: 2017-05-12Bibliographically approved

Open Access in DiVA

fulltext(1371 kB)62 downloads
File information
File name FULLTEXT01.pdfFile size 1371 kBChecksum SHA-512
93ed42728fed002bfa2d9bf5e143eeda2d24b1dc557f84a6c95a4683ccfc4f2f0f51558672738cd914510396b33b7430b2f00e377d7c912e88f045891508a59e
Type fulltextMimetype application/pdf

Other links

Publisher's full text

Search in DiVA

By author/editor
Unnikrishnan, VishnuVesterbacka, Mark
By organisation
Integrated Circuits and SystemsFaculty of Science & Engineering
In the same journal
IEEE Transactions on Circuits and Systems Part 1: Regular Papers
Signal ProcessingEmbedded SystemsComputer EngineeringTelecommunications

Search outside of DiVA

GoogleGoogle Scholar
Total: 62 downloads
The number of downloads is the sum of all downloads of full texts. It may include eg previous versions that are now no longer available

Altmetric score

Total: 826 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf