LiU Electronic Press
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Author:
Larsson, Anders (Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory) (Linköping University, The Institute of Technology)
Title:
Test Optimization for Core-based System-on-Chip
Department:
Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory
Linköping University, The Institute of Technology
Publication type:
Doctoral thesis, monograph (Other academic)
Language:
English
Place of publ.: Linköping Publisher: Linköping University Electronic Press
Distributor:
Institutionen för datavetenskap
Pages:
189
Series:
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524; 1222
Year of publ.:
2008
URI:
urn:nbn:se:liu:diva-15182
Permanent link:
http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-15182
ISBN:
978-91-7393-768-9
Subject category:
Computer Science
SVEP category:
Computer science
Abstract(en) :

The semiconductor technology has enabled the fabrication of integrated circuits (ICs), which may include billions of transistors and can contain all necessary electronic circuitry for a complete system, so-called System-on-Chip (SOC). In order to handle design complexity and to meet short time-to-market requirements, it is increasingly common to make use of a modular design approach where an SOC is composed of pre-designed and pre-verified blocks of logic, called cores.

Due to imperfections in the fabrication process, each IC must be individually tested. A major problem is that the cost of test is increasing and is becoming a dominating part of the overall manufacturing cost. The cost of test is strongly related to the increasing test-data volumes, which lead to longer test application times and larger tester memory requirement. For ICs designed in a modular fashion, the high test cost can be addressed by adequate test planning, which includes test-architecture design, test scheduling, test-data compression, and test sharing techniques.

In this thesis, we analyze and explore several design and optimization problems related to core-based SOC test planning. We perform optimization of test sharing and test-data compression. We explore the impact of test compression techniques on test application time and compression ratio. We make use of analysis to explore the optimization of test sharing and test-data compression in conjunction with test-architecture design and test scheduling. Extensive experiments, based on benchmarks and industrial designs, have been performed to demonstrate the significance of our techniques.

Public defence:
2008-11-12, Visionen, hus B, Campus Valla, Linköpings universitet, Linköping, 13:15 (English)
Degree:
Doctor of Philosophy (PhD)
Supervisor:
Larsson, Erik, Assistant Professor (Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory) (Linköping University, The Institute of Technology)
Peng, Zebo, Professor (Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory) (Linköping University, The Institute of Technology)
Ion Eles, Petru, Professor (Linköping University, Department of Computer and Information Science)
Opponent:
Nicolici, Nicola, Dr. (McMaster University, Ontario, Canada)
Available from:
2008-10-22
Created:
2008-10-22
Last updated:
2009-05-05
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