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Schedulability and Memory Interference Analysis of Multicore Preemptive Real-time Systems
Linköping University. (RTSLAB)
Linköping University, Department of Computer and Information Science, Software and Systems. (RTSLAB)
2017 (English)In: 8th ACM/SPEC International Conference on Performance Engineering (ICPE), 2017Conference paper, Published paper (Refereed)
Place, publisher, year, edition, pages
2017.
Keyword [en]
Schedulability, Memory interference, Multicore systems, model checking
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-141783DOI: 10.1145/3030207.3030233OAI: oai:DiVA.org:liu-141783DiVA: diva2:1147460
Conference
8th ACM/SPEC International Conference on Performance Engineering (ICPE)
Projects
NFFP6
Available from: 2017-10-05 Created: 2017-10-05 Last updated: 2017-10-05

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Linköping UniversitySoftware and Systems
Engineering and Technology

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CiteExportLink to record
Permanent link

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Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf