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Schedulability and Memory Interference Analysis of Multicore Preemptive Real-time Systems
Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering. (RTSLAB)
Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering. (RTSLAB)ORCID iD: 0000-0002-1485-0802
2017 (English)In: ICPE '17 Proceedings of the 8th ACM/SPEC on International Conference on Performance Engineering, ACM Press, 2017, p. 263-274Conference paper, Published paper (Refereed)
Abstract [en]

Today's embedded systems demand increasing computing power to accommodate the ever-growing software functionality. Automotive and avionic systems aim to leverage the high performance capabilities of multicore platforms, but are faced with challenges with respect to temporal predictability. Multicore designers have achieved much progress on improvement of memory-dependent performance in caching systems and shared memories in general. However, having applications running simultaneously and requesting the access to the shared memories concurrently leads to interference. The performance unpredictability resulting from interference at any shared memory level may lead to violation of the timing properties in safety-critical real-time systems. In this paper, we introduce a formal analysis framework for the schedulability and memory interference of multicore systems with shared caches and DRAM. We build a multicore system model with a fine grained application behavior given in terms of periodic preemptible tasks, described with explicit read and write access numbers for shared caches and DRAM. We also provide a method to analyze and recommend candidates for task-to-core reallocation with the goal to find schedulable configurations if a given system is not schedulable. Our model-based framework is realized using Uppaal and has been used to analyze a case study.

Place, publisher, year, edition, pages
ACM Press, 2017. p. 263-274
Keywords [en]
Schedulability, Memory interference, Multicore systems, model checking
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-141783DOI: 10.1145/3030207.3030233ISBN: 978-1-4503-4404-3 OAI: oai:DiVA.org:liu-141783DiVA, id: diva2:1147460
Conference
8th ACM/SPEC International Conference on Performance Engineering (ICPE), L'Aquila, Italy — April 22 - 26, 2017
Projects
NFFP6Available from: 2017-10-05 Created: 2017-10-05 Last updated: 2018-08-14

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CiteExportLink to record
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Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf