liu.seSearch for publications in DiVA
Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Background radiation and soft errors in CMOS circuits
Linköping University, Department of Physics, Chemistry and Biology. Linköping University, The Institute of Technology. Univ.,.
2000 (English)Doctoral thesis, monograph (Other academic)
Abstract [en]

Background radiation in natural environments from ground level to airplane flight altitudes consists of electrons, neutrons, protons, pions, muons, and other types of particles. These particles originate either from cosmic rays or from radioactive decay. Energy of a single particle can be large enough to charge or discharge a circuit node, which can be observed as a faulty bit stored in a memory or latch. This type of error is called soft error, because it results in a loss of information, as opposed to a hard error, which results in physical damage of a device.

This thesis reports on soft errors in digital CMOS circuits. The dominating source of soft errors in environments from ground level to airplane flight altitudes are atmospheric neutrons. The goal is to determine the error probability for present-day technologies, and to estimate the trend in soft error sensitivity with advancing technology scaling.

Voltage dependence of the neutron-induced soft error rate (SER) was investigated for a static memory. Custom test chips were designed in a 0.8 μm process and tested at accelerator facilities. The measurements showed an increase in SER at reduced supply voltages. A comparison with SER calculated from a BGR model did not give satisfactory results, and showed a need for more accurate modeling and measurements.

A new empirical model was proposed. The model takes into account the SER dependence on the transistor type, signal charge, supply voltage, and time characteristics of induced noise. The model needed to be calibrated by SER measurements.

For this purpose, a novel test circuit was designed and implemented in a 0.6 μm process. The test circuit was calibrated by a new measurement method with accuracy of 2%. The SER measurements were taken at the Los Alamos National Laboratory, New Mexico. The empirical model was calibrated for the 0.6 μm process and the atmospheric neutron spectrum. The model was verified by independent measurements on a correlator chip, and by finite-element device simulations.

Also, probability of simultaneous double error rate, and its dependence on voltage and charge were measured. These results have implications for application of error correcting codes and redundant circuit techniques.

The model was also calibrated by SER measurements at the The Svedberg Laboratory (TSL), Sweden. A comparison between the atmospheric and the TSL model showed, that although the TSL spectrum is different from the atmospheric one, the TSL neutron beam can be used for SER testing.

Device simulations were used to translate the empirical model from the 0.6 μm

technology to the 0.8, 0.35, and 0.1 μm technologies. A scaling theory for the atmospheric neutron SER was developed, which takes into account the substrate doping, supply voltage, time characteristics, transistor performance, and physical dimensions. A trend in the SER of a static memory is predicted.

This thesis draws important conclusions about soft-error reliability of CMOS circuits. At sea level, a 1 Mbit static memory fabricated in a 0.6 μm process experiences one error approximately each 160 years. When the same memory is operated onboard an airplane, one error occurs approximately each year. If the supply voltage is reduced from 5 V to 3.3 V, then the error frequency increases four times. Moreover it can be expected, that up to 12% of errors affect simultaneously more than one bit. A 1 Mbit memory implemented in a future 0.1 μm process will be four times more reliable than a 1 Mbit memory implemented in a 0.6 μm process. On the other hand, a future static memory is likely to increase in size to about 32 Mbit, which will result in a total increase of error frequency by a factor of eight. In conclusion, atmospheric neutron soft error rate increases approximately linearly with decreasing technology feature size. A 32 Mbit static memory implemented in a 0.1 μm process will fail on the average each 5.7 years at sea level, or each 20 days at airplane flight altitudes. The same trend should apply also to other logic circuits, e.g. flip-flops, latches, registers, but also combinational circuits.

Place, publisher, year, edition, pages
Linköping: Linköpings universitet , 2000. , p. 124
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 638
National Category
Natural Sciences
Identifiers
URN: urn:nbn:se:liu:diva-143510ISBN: 9172197935 (print)OAI: oai:DiVA.org:liu-143510DiVA: diva2:1164488
Public defence
2000-09-29, Planck, IFM, Campus Valla, Linköping, 13:15 (English)
Available from: 2017-12-11 Created: 2017-12-11 Last updated: 2018-01-09Bibliographically approved

Open Access in DiVA

No full text in DiVA

By organisation
Department of Physics, Chemistry and BiologyThe Institute of Technology
Natural Sciences

Search outside of DiVA

GoogleGoogle Scholar

isbn
urn-nbn

Altmetric score

isbn
urn-nbn
Total: 4 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf