SiC has emerged as a promising semiconductor to replace Si in high power, high frequency and high temperature electronics. Thanks ¹to the advantageous intrinsic material properties, such as large band gap, high electric breakdown field, high thermal conductivity and highly inert chemical properties, intensified efforts world-wide have been attracted in developing crystal growth technology and device fabrication processes for the SiC components. As a result of the fast progress in the crystal growth technology, up to 3 inch n-type and 2 inch both n- and p-type SiC substrates, grown by seeded sublimation technique, are now commercially available. The substrate quality is under constant improvement in terms of micropipe density and structural perfection. In this context, a new crystal growth technique using high temperature chemical vapour deposition (HTCVD) has accelerated the improvement of substrate quality and demonstrated great potential for producing high quality semi-insulating SiC substrates.

For SiC device fabrication, CVD has been the technique of choice for producing epitaxial structures. For kV-class high power devices, thick and low-doped epilayers with high crystalline quality are required. To meet this requirement, a fast epitaxy technique has been developed in a vertical, hot-wall reactor, also known as a chimney reactor. Compared with the growth rate of 2 - 6 μm/h from the convention CVD in the horizontal hot-wall reactor, the chimney process has produced epilayers with growth rates as high as 10 - 40 μm/h and residual doping of low 1013 - 10 15 cm-3 • Edge-terminated Schottky diodes made on the chimney-grown epilayers have demonstrated a reverse blocking voltage of 3.85 kV. The system design concern of the chimney reactor and the characteristics of the fast epitaxy technique are presented in Paper 1. The growth behaviour in the vertical hot-wall reactor in both up- and down-orientations is further exploited in Paper 2. The nitrogen doping behaviour and the morphology control of the thick epilayers are investigated in Papers 3 and 4. In paper 5, the electrically active impurities in these epilayers are characterised using Deep Level Transient Spectrometry (DLTS). The influence of the growth conditions on these defects is studied.

 For low-power or high frequency devices such as MESFETs, the CVD process developed in a horizontal hot-wall reactor has shown to be capable of matching the specific demands imposed by these devices. During the process development in this reactor, the pre-growth etching of the substrate has shown to improve the morphology of the subsequently grown epilayers. A detailed study of the in situ etching mechanism has been carried out and the results are presented in Paper 6. To significantly increase the uniformity and the throughput, gas foil rotation has been installed in this reactor, providing a capacity of 3x2" wafers. The first results of the epilayers grown with the gas foil rotation in the horizontal hot-wall CVD reactor is reported in Paper 7.