In this thesis we discuss design and implementation of low-complexity digital filters. Digital filters are key components in many digital signal processing (DSP) systems. Typical applications include interpolation, decimation, and noise suppression.

The work presented in the thesis can be divided into four parts.

In the first part, we consider implementation of wave digital filters using bit-and digit-serial arithmetic. Scheduling formulations to obtain maximally fast (or rate optimal) implementations are presented for a number of lattice wave digital filters. By using a numerically equivalent state-space representation a similar approach is introduced for ladder wave digital filters. It is shown that maximally fast implementations also can be obtained using distributed arithmetic. Furthermore, the optimal degree of logic level pipelining is derived for maximal sample rate.

In the second part, a novel class of frequency-response masking filters is introduced. The filter structures use identical subfilters and, thereby, a lowcomplexity, pipeline/interleaved, implementation can be obtained using folding. By using frequency-response masking techniques the number of multipliers required is decreased for FIR filters and the maximal sample rate is increased for IIR filters.

 The problems of single and multiple constant multiplication (SCM and MCM) are discussed in the third part. When the multiplication coefficient is constant it is possible to reduce the number of additions required compared to a general coefficient multiplication. Furthermore, it is possible to utilize redundant subexpressions when one data is multiplied with multiple constant coefficients. For the single multiplier case, a novel graph formulation is introduced that decreases the search space required for optimum design. For the MCM problem two novel solutions are introduced. One is based on integer linear programming (ILP) and can be integrated with the design of linear- phase FIR filters. The other is based on minimum spanning trees (MSTs) and, as such, the solution time is polynomial in the number of coefficients. Furthermore, both the SCM and MCM problems are considered using high-speed redundant carry-save adders, and solutions are proposed.

Finally, in the fourth part, the design of linear-phase FIR filters using mixed integer linear programming (MILP) is discussed. Here, we minimize the arithmetic complexity given a filter specification. Problems are formulated for minimum number of signed-power-of-two (SPT) terms in the coefficients, minimum number of adders in the complete filter, and minimum total Hamming distance between adjacent coefficients. The last approach is suitable for low-power implementation on multiply-and-accumulate (MAC) architectures, e.g., DSP processors.