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An RNS Based Modular Multiplier with Reduced Complexity
Western Sydney Univ, Australia.
Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
2017 (English)In: 2017 IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS): NORCHIP AND INTERNATIONAL SYMPOSIUM OF SYSTEM-ON-CHIP (SOC), IEEE , 2017Conference paper, Published paper (Refereed)
Abstract [en]

Modular multiplication (MM) based on the residue number system (RNS) is a widely researched area due to the fast arithmetic operations in the RNS. The major drawback of the RNS based MM architectures is their large area because each arithmetic operation is followed by a modular reduction. In this work, the number of modular reductions is reduced and instead the wordlength of some operations is increased to accommodate the intermediate results. The proposed scheme greatly reduces the number of multipliers and achieves a 55% reduction in the hardware complexity. Moreover the delay of the proposed architecture is also significantly lower than the reference architecture.

Place, publisher, year, edition, pages
IEEE , 2017.
National Category
Computer Engineering
Identifiers
URN: urn:nbn:se:liu:diva-145839DOI: 10.1109/NORCHIP.2017.8124953ISI: 000425049100012ISBN: 978-1-5386-2844-7 OAI: oai:DiVA.org:liu-145839DiVA, id: diva2:1192080
Conference
IEEE Nordic Circuits and Systems Conference (NORCAS) / NORCHIP and International Symposium of System-on-Chip (SoC)
Available from: 2018-03-21 Created: 2018-03-21 Last updated: 2018-03-21

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  • apa
  • harvard1
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  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
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  • asciidoc
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