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Ring-oscillator-based timing generator for ultralow-power applications
Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.ORCID iD: 0000-0003-2056-4762
Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
2017 (English)In: 2017 IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS): NORCHIP AND INTERNATIONAL SYMPOSIUM OF SYSTEM-ON-CHIP (SOC), IEEE , 2017Conference paper, Published paper (Refereed)
Abstract [en]

Many integrated circuit functional blocks, such as data and power converters, require timing and control signals consisting of complex sequences of pulses. Traditionally, these signals are generated from a clock signal using a combination of flip-flops, latches and delay elements. Due to the large internal switching activity of flips-flops and due to the many, effectively unused, clock cycles, this solution is inefficient from a power consumption point of view and is, therefore, unsuitable for ultralow-power applications. In this paper we present a method to generate non-overlapping control signals without using flip-flops or a clock. We propose to decode and translate the internal states of a ring oscillator into the desired control signal sequence. We show how this can be achieved using a simple combinatorial logic decoder. The proposed architecture significantly reduces the switching activity and the capacitive load, largely reducing the consumed power. We show an example implementation of a 9-bit SAR logic utilizing our proposed method. Furthermore, we show simulation results and compare the power consumption of the example SAR implementation to that of a functionally identical flip-flop-based state-of-the-art ultralow-power SAR. We were able to achieve a 5.8x reduction in consumed power for the complete SAR and 8x for the one-hot generation sub-part.

Place, publisher, year, edition, pages
IEEE , 2017.
Keywords [en]
timing generation; sequence generation; clock; state machine; ultralow power; low power; ring oscillator; SAR ADC
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-145838DOI: 10.1109/NORCHIP.2017.8124969ISI: 000425049100026ISBN: 978-1-5386-2844-7 OAI: oai:DiVA.org:liu-145838DiVA, id: diva2:1192099
Conference
IEEE Nordic Circuits and Systems Conference (NORCAS) / NORCHIP and International Symposium of System-on-Chip (SoC)
Note

Funding Agencies|European Unions Horizon project smart-MEMPHIS [644378]; strategic innovation program Smarter Electronics Systems a joint venture of Swedens innovation agency, Swedish Research Council Formas; Swedish Energy Agency [2015-01305]

Available from: 2018-03-21 Created: 2018-03-21 Last updated: 2018-03-21

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CiteExportLink to record
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Citation style
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