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A Low Noise RC-based Phase Interpolator in 16-nm CMOS
Huawei Technologies Sweden AB, Kista, Sweden.
Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, Faculty of Science & Engineering.ORCID iD: 0000-0003-2117-1178
Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, Faculty of Science & Engineering.
2019 (English)In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 66, no 1Article in journal (Refereed) Published
Abstract [en]

This paper describes a passive analog phase interpolator, utilizing a switched RC-network. The proposed circuit eliminates the current sources in a phase interpolator based on constant-slope charging. By eliminating the current source, the noise is significantly reduced due to the reduction in thermal and flicker noise. The phase interpolator has a resolution of 6 bits and is implemented in a 16-nm CMOS process. The maximum differential non-linearity is measured to be 0.1 LSBs at a 192 ps input time delta. The circuit draws 0.2 mW from a 0.8 V supply, and occupies 0.004 mm2.

Place, publisher, year, edition, pages
2019. Vol. 66, no 1
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-147285DOI: 10.1109/TCSII.2018.2823902ISI: 000454341300001OAI: oai:DiVA.org:liu-147285DiVA, id: diva2:1197563
Available from: 2018-04-13 Created: 2018-04-13 Last updated: 2019-01-11

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Serban, AdrianaGong, Shaofang

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CiteExportLink to record
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Citation style
  • apa
  • ieee
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  • de-DE
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