In this thesis we discuss various issues involving the design path for low power design of frequency-selective digital filters. As recursive filters have a bound on the minimal iteration period, Tmin we focus on these. Implementations that obtain Tmin are known as maximally fast.
The main idea to obtain a low power implementation is to use a maximally fast implementation and trade any excess speed for lower power consumption by decreasing the power supply voltage.
We show that using three-port adaptor allpass sections and constrained third-order allpass sections for implementation of maximally fast lattice wave digital filters are advantageous compared with second-order Richards' structures.
We further show that maximally fast ladder wave digital filters can be efficiently implemented using the same techniques as for lattice wave digital filters, despite that they have a more complex structure with many loops.
We also show that maximally fast digital filters can be implemented using a numerically equivalent state-space representation and distributed arithmetic. As the latency of distributed arithmetic is dependent on the number of fractional bits of the longest coefficient, it may decrease the performance if the critical loop is through one of the shorter coefficients. However, we show that by modifying the contents of the ROM we can achieve Tmin independent of the other coefficients in the ROM.
Further, we introduce single filter frequency masking. In this approach we substitute the different subfilters in narrow-band frequency masking and frequency-response masking structures to identical subfilters (except for the periodicity). By mapping the subfilters to the same hardware structure using folding an efficient hardware implementation is obtained. This approach is discussed for narrow-band lowpass recursive and FIR filters, and for frequency-response masking structures based on FIR filters.
Linköping: Linköpings universitet , 2000. , p. 110