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CMOS mixed analog/digital building blocks for signal processing
Linköping University, Department of Physics, Measurement Technology, Biology and Chemistry. Linköping University, The Institute of Technology.
1999 (Swedish)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

A mixed analog/digital multiply-accumulate unit is presented. The unit is composed of the multiplying D/A converter and a polarity switching network. It is featured by an analog continuous-time input port, a discrete­time output port, and a digital input port for the quantized multiplying coefficient. This unit constitute a core for mixed analog-digital computations, and its versatility can be compared to the all-digital multiply-accumulate unit. Mixed-signal computations is useful in environments where the input signals are analog in nature, but where signal processing in the digital domain is desired. A traditional system adapted for such an environment consist of an A/D converter, followed by digital signal processing elements, or a digital signal processor. It is shown that the system power drain can be reduced considerable if using the mixed analog/digital MAC unit followed by an A/D converter instead of the former configuration. This is true when the signal processing task reduces the required A/D conversion rate or accuracy, and when a low number of MAC units are required, since the complexity (chip area) of such units are considerable.

Some proposed suitable signal processing tasks are pattern matching (not shown in the thesis) and narrow­band PIR filtering followed by decimation, which possibly are suitable for radio receiver applications. A design methodology for the realization of PIR filters suitable for implementation with a low number of MAC units is given. Mixed analog/digital MAC units have been designed with 1-bit and 8-bit coefficient resolution respectively and implemented in a double-poly 0.6µm CMOS process. Chip measurements have verified high performance of the 1-bit mixed analog/digital MAC unit, but the 8-bit counterpart still suffers from imperfections of unknown origin. The consequence of the imperfections show up as a coefficient dead zone.

The bottom-plate sample-and-hold circuit is analyzed with simulations. It is shown that the track-mode linearity depends on the analog input frequency. If the track-mode linearity, the hold-mode introduced thermal noise, and the desired bandwidth as a fraction of the Nyquist frequency is considered - maximum spurious­free dynamic range, is achieved with a low bias voltage, and with a low input voltage swing.

Place, publisher, year, edition, pages
Linköping: Linköpings universitet , 1999. , p. 34
Series
Linköping Studies in Science and Technology. Thesis, ISSN 0280-7971 ; 801
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-145899Libris ID: 7624460Local ID: LiU-TEK-LIC-1999:59ISBN: 9172196505 (print)OAI: oai:DiVA.org:liu-145899DiVA, id: diva2:1201191
Available from: 2018-04-25 Created: 2018-04-25 Last updated: 2023-03-14Bibliographically approved

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Duppils, Mattias

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  • apa
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