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Shift‐Add Circuits for Constant Multiplications
Independent Hardware Consultant.
Nanyang Technological University, Singapore, Singapore.
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering.ORCID iD: 0000-0003-3470-3911
Nanyang Technological University, Singapore, Singapore.
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2017 (English)In: Arithmetic Circuits for DSP Applications / [ed] Pramod Kumar Meher, Thanos Stouraitis, John Wiley & Sons, 2017, p. 33-76Chapter in book (Other academic)
Abstract [en]

The optimization of shift‐and‐add network for constant multiplications is found to have great potential for reducing the area, delay, and power consumption of implementation of multiplications in several computation‐intensive applications not only in dedicated hardware but also in programmable computing systems. To simplify the shift‐and‐add network in single constant multiplication (SCM) circuits, this chapter discusses three design approaches, including direct simplification from a given number representation, simplification by redundant signed digit (SD) representation, and simplification by adder graph. Examples of the multiple constant multiplication (MCM) methods are constant matrix multiplication, discrete cosine transform (DCT) or fast Fourier transform (FFT), and polyphase finite impulse response (FIR) filters and filter banks. The given constant multiplication methods can be used for matrix multiplications and inner‐product; and can be applied easily to image/video processing and graphics applications. The chapter further discusses some of the shortcomings in the current research on constant multiplications, and possible scopes of improvement.

Place, publisher, year, edition, pages
John Wiley & Sons, 2017. p. 33-76
Keywords [en]
adder graph, constant multiplication methods, fast Fourier transform, polyphase finite impulse response filters, programmable computing systems, redundant signed digit representation, shift‐add circuits
National Category
Computer Systems Embedded Systems Signal Processing
Identifiers
URN: urn:nbn:se:liu:diva-150919DOI: 10.1002/9781119206804.ch2ISBN: 9781119206774 (print)ISBN: 9781119206798 (electronic)ISBN: 9781119206804 (print)OAI: oai:DiVA.org:liu-150919DiVA, id: diva2:1245407
Available from: 2018-09-05 Created: 2018-09-05 Last updated: 2018-09-05Bibliographically approved

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Gustafsson, Oscar

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CiteExportLink to record
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Citation style
  • apa
  • harvard1
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  • Other style
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Language
  • de-DE
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  • en-US
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  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
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