The development of integrated circuits is continuously moving towards a System-on­ Chip realization where global interconnects, connecting circuit blocks separated by a long distance, have been considered a showstopper for process scaling due to their RC-delays. Our knowledge today is that high-speed interconnects must be described by models which include not only R and C, but also inductance and skin effect. One might think that this will make the situation worse, but we show that it is not so.

In this thesis, we investigate the relevance of inductance in interconnect models and propose a new scheme for global interconnects based on the utilization of microstrip lines using two upper-level metal layers, one thicker layer for wires and one for a return ground plane. We are concerned with key performance measures such as data delay, maximum data-rate, crosstalk, edge-rates and power dissipation. Using our approach, we show that well-designed, highly lossy, long interconnects may show reasonable delays of the order of twice the delay compared to the velocity of light delay, and allow high data rates disconnected from total delay through wave pipelining. To demonstrate the feasibility of the proposed concept, we have designed and fabricated a test chip carrying a 5 mm long global communication link. Measurements show that we can achieve 3 Gb/s/wire over this 5 mm long, repeaterless on-chip bus implemented in a standard 0.18 µm CMOS process, achieving a signal velocity of 1/3 of the velocity of light in vacuum.

In the context of technology scaling, there is a tendency for interconnects to dominate chip power dissipation due to their large total capacitance. In this thesis we address the problem of interconnect power dissipation by proposing and analyzing a transition­ energy cost model aimed for efficient power estimation of performance-critical buses. The model, which includes properties that closely capture effects present in high­ performance VLSI buses, can be used to more accurately determine energy benefits of e.g. transition coding of bus topologies. We further show a power optimization scheme based on appropriate choice of reduced voltage swing of the interconnect and scaling of receiver amplifier. Finally, the power saving impact of swing reduction in combination with a sense-amplifying flip-flop receiver is shown on a cache bus architecture used in industry.