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Flit Synchronous Aelite Network on Chip
Linköping University, Department of Electrical Engineering.
2008 (English)Independent thesis Advanced level (professional degree), 20 credits / 30 HE creditsStudent thesis
Abstract [en]


The deep sub micron process technology and application convergence increases the design challenges in System-on-Chip (SoC). The traditional bus based on chip communication are not scalable and fails to deliver the performance requirements of the complex SoC. The Network on Chip (NoC) has been emerged as a solution to address these complexities of a efficient, high performance, scalable SoC design. The Aethereal NoC provides the latency and throughput bounds by pipelined timedivision multiplexed (TDM) circuit switching architecture. A global synchronous clock defines the timing for TDM, which is not beneficial for decreasing process geometry and increasing clock frequency. This thesis work focuses on the Aelite NoC architecture. The Aelite NoC offering guaranteed services exploits the complexities of System-on-Chip design with real time requirements. The Aelite NoC implements flit synchronous communication using mesochronous and asynchronous links.



Place, publisher, year, edition, pages
2008. , 56 p.
Network on Chip, Mesochronous, GALS
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
URN: urn:nbn:se:liu:diva-15895ISRN: LiTH-ISY-EX--08/4198--SEOAI: diva2:128060
Nollstället, Hus B, Campus Valla, Linköpings univeristet, Linkoping (English)
Available from: 2008-12-11 Created: 2008-12-11 Last updated: 2008-12-31Bibliographically approved

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