This thesis describes an attempt to formalize the design process of VLSI systems as a sequence of semantics-preserving mappings which transforms a program-like behavioral description into a structural description. The produced structural description may then be partitioned into several potential asynchronous modules with well-defined interfaces. The proposed strategy is based on a formal computational model derived from timed Petri net and consisting of separate, but related, models of control and data parts. Partitioning of systems into submodules is provided both on the data part and on the control part, which produces a set of pairs of corresponding data subparts and control subparts and allows potential asynchronous operation of the designed systems as well as physical distribution of the modules. The use of such a formal specification also leads to the effective use of CAD and automatic tools in the synthesis process as well as providing for the possibility of verifying some aspects of a design before it is completed. CAMAD, an integrated design aid system, has been partially developed based on these formalizations. The present thesis attempts also to formulate the control/data path allocation and module partitioning problem as an optimization problem. This differs from previous approaches where ad hoc algorithms and predefined implementation structures are explicitly or implicitly used, and where a centralized control strategy is assumed.