Model validation for embedded systems using formal method-aided simulation
2008 (English)In: IET Computers and digital techniques, ISSN 1751-8601 , Vol. 2, no 6, 413-433 p.Article in journal (Refereed) Published
Embedded systems are becoming increasingly common in our everyday lives. As technology progresses, these systems become more and more complex. At the same time, the systems must fulfil strict requirements on reliability and correctness. Informal validation techniques, such as simulation, suffer from the fact that they only examine a small fraction of the state space. Therefore simulation results cannot be 100% guaranteed. Formal techniques, on the other hand, suffer from state-space explosion and might not be practical for huge, complex systems due to memory and time limitations. A validation approach, based on simulation, which addresses some of the above problems is proposed. Formal methods, in particular, model checking, are used to aid, or guide, the simulation process in certain situations in order to boost coverage. The invocation frequency of the model checker is dynamically controlled by estimating certain parameters related to the simulation speed of the particular system at hand. These estimations are based on statistical data collected during the validation session, in order to minimise veri. cation time, and at the same time, achieve reasonable coverage.
Place, publisher, year, edition, pages
2008. Vol. 2, no 6, 413-433 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-16215DOI: 10.1049/iet-cdt:20070128OAI: oai:DiVA.org:liu-16215DiVA: diva2:133458
This paper is a postprint of a paper submitted to and accepted for publication in IET COMPUTERS AND DIGITAL TECHNIQUES and is subject to Institution of Engineering and Technology Copyright. The copy of record is available at IET Digital Library
Daniel Karlsson, Petru Ion Eles and Zebo Peng, Model validation for embedded systems using formal method-aided simulation, 2008, IET COMPUTERS AND DIGITAL TECHNIQUES, (2), 6, 413-433.