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Electrical Characterisation of Thick 3C-SiC Layers Grown on Off-Axis 4H-SiC Substrates
University of Warwick, Coventry, United Kingdom.
Linköping University, Department of Physics, Chemistry and Biology, Semiconductor Materials. Linköping University, Faculty of Science & Engineering.
University of Warwick, Coventry, United Kingdom.
Linköping University, Department of Physics, Chemistry and Biology, Semiconductor Materials. Linköping University, Faculty of Science & Engineering.
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2019 (English)In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 963, p. 353-356Article in journal (Refereed) Published
Abstract [en]

300 μm thick 3C-SiC epilayer was grown on off-axis 4H-SiC(0001) substrate with a high growth rate of 1 mm/hour. Dry oxidation, wet oxidation and N2O anneal were applied to fabricate lateral MOS capacitors on these 3C-SiC layers. MOS interface obtained by N2O anneal has the lowest interface trap density of 3~4x1011 eV-1cm-2. Although all MOS capacitors still have positive net charges at the MOS interface, the wet oxidised sample has the lowest effective charge density of ~9.17x1011 cm-2.

Place, publisher, year, edition, pages
Trans Tech Publications, 2019. Vol. 963, p. 353-356
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Condensed Matter Physics
Identifiers
URN: urn:nbn:se:liu:diva-160225DOI: 10.4028/www.scientific.net/MSF.963.353Scopus ID: 2-s2.0-85071861789OAI: oai:DiVA.org:liu-160225DiVA, id: diva2:1350666
Available from: 2019-09-11 Created: 2019-09-11 Last updated: 2019-09-17Bibliographically approved

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Jokubavicius, ValdasYakimova, Rositsa

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