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Test Flow Selection for Stacked Integrated Circuits
Lund Univ, Sweden.
Lund Univ, Sweden.
Linköping University.
Lund Univ, Sweden.
2019 (English)In: Journal of electronic testing, ISSN 0923-8174, E-ISSN 1573-0727, Vol. 35, no 4, p. 425-440Article in journal (Refereed) Published
Abstract [en]

Integrated circuits (ICs) with a single chip (die) are typically tested with a test flow consisting of two test instances: (1) wafer sort for the bare chip and (2) package test for the packaged IC. For ICs with stacked chips - 3D Stacked ICs - there are many possible test instances, even more test flows, and no commonly used test flow. In this paper, we propose a test flow selection algorithm (TFSA) to obtain a test flow for a given 3D Stacked IC. The TFSA results in a test flow for a given 3D Stacked IC, such that the expected total test time to produce each good package is minimized. We implemented the TFSA, three straightforward test flow schemes and an exhaustive search, and experimentally compared the test flow schemes on three different test architecture design approaches. The results demonstrate the importance to have methods both to select the test flow and design the test architecture.

Place, publisher, year, edition, pages
Springer-Verlag New York, 2019. Vol. 35, no 4, p. 425-440
Keywords [en]
3D IC; Stacked integrated circuits; Test flow; Test time; Yield; Test plan; IEEE 1500; Test architecture; Expected time; Effective yield; Quantity
National Category
Computer Sciences
Identifiers
URN: urn:nbn:se:liu:diva-160622DOI: 10.1007/s10836-019-05813-zISI: 000484925000002Scopus ID: 2-s2.0-85070884880OAI: oai:DiVA.org:liu-160622DiVA, id: diva2:1362624
Available from: 2019-10-21 Created: 2019-10-21 Last updated: 2019-10-28Bibliographically approved

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Dash, Assmitra
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CiteExportLink to record
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Citation style
  • apa
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  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
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  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf