High-level synthesis deals with the problem of transforming a behavioral description of a design into a register transfer level implementation. This enables the specification of designs at a high level of abstraction. However, designs with timing requirements can not be implemented in this way, unless there is a way to include the timing requirements in the behavioral specification. Local timing constraints (LTCs) enable the designer to specify the time between the execution of operations and more closely model the external behavior of a design. This thesis deals with the modelling of LTCs and the process of high-level synthesis under LTCs.Since high-level synthesis starts from behavioral specifications an approach to transfer LTCs from behavioral VHDL to an intermediate design representation has been adopted. In the intermediate design representation the LTCs are modelled in such a way that they can be easily analyzed and interpreted. Before the high-level synthesis process is started a consistency check is carried out to discover contradictions between the specified LTCs.If the LTCs are consistent a preliminary scheduling of the operations can be performed and the clock period decided. For that purpose two different approaches, based on unicycle and multicycle scheduling, have been developed. The unicycle scheduling approach assumes that the longest delay between two registers equals the clock period. Design transformations are used to change the number of serialized operations between the registers and, thus, change the clock period to satisfy the LTCs. The multicycle scheduling approach allows the longest delay between two registers to be several clock periods long. Thus, the goal is to find a reasonable clock period and a preliminary schedule that satisfy the LTCs. Furthermore, the multicycle scheduling approach does trade-offs between speed and cost (silicon area) when deciding on which modules to be used to implement the operations. Both Genetic algorithms and Tabu search are used to solve the combinatorial optimization problem that arises during the multicycle scheduling.If the preliminary schedule fulfills all the LTCs then module allocation and binding is performed. The goal is to perform all the operations while using as few functional modules as possible. This is achieved by module sharing. Experimental results show that the high-level synthesis performed by the proposed methods produces efficient designs.