In this paper, we present a new approach to simplify fast Fourier transform (FFT) hardware architectures. The new approach is based on a group of transformations called decimation, reduction, center, move and merge. By combining them it is possible to transform the rotators at different FFT stages, move them to other stages and merge them in such a way that the resulting rotators are simpler than the original ones. The proposed approach can be combined with other existing techniques such coefficient selection and shift-and-add implementation, or rotator allocation in order to obtain low-complexity FFT hardware architectures. To show the effectiveness of the proposed approach, it has been applied to single-path delay feedback (SDF) FFT hardware architectures, where it is observed that the complexity of the rotators is reduced up to 33%.