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Performance driven FPGA design with an ASIC perspective
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.ORCID iD: 0000-0002-0111-2384
2009 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

FPGA devices are an important component in many modern devices. This means that it is important that VLSI designers have a thorough knowledge of how to optimize designs for FPGAs. While the design flows for ASICs and FPGAs are similar, there are many differences as well due to the limitations inherent in FPGA devices. To be able to use an FPGA efficiently it is important to be aware of both the strengths and oweaknesses of FPGAs. If an FPGA design should be ported to an ASIC at a later stage it is also important to take this into account early in the design cycle so that the ASIC port will be efficient.

This thesis investigates how to optimize a design for an FPGA through a number of case studies of important SoC components. One of these case studies discusses high speed processors and the tradeoffs that are necessary when constructing very high speed processors in FPGAs. The processor has a maximum clock frequency of 357~MHz in a Xilinx Virtex-4 devices of the fastest speedgrade, which is significantly higher than Xilinx' own processor in the same FPGA.

Another case study investigates floating point datapaths and describes how a floating point adder and multiplier can be efficiently implemented in an FPGA.

The final case study investigates Network-on-Chip architectures and how these can be optimized for FPGAs. The main focus is on packet switched architectures, but a circuit switched architecture optimized for FPGAs is also investigated.

All of these case studies also contain information about potential pitfalls when porting designs optimized for an FPGA to an ASIC. The focus in this case is on systems where initial low volume production will be using FPGAs while still keeping the option open to port the design to an ASIC if the demand is high. This information will also be useful for designers who want to create IP cores that can be efficiently mapped to both FPGAs and ASICs.

Finally, a framework is also presented which allows for the creation of custom backend tools for the Xilinx design flow. The framework is already useful for some tasks, but the main reason for including it is to inspire researchers and developers to use this powerful ability in their own design tools.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press , 2009. , 165 p.
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1237
Keyword [en]
FPGA Optimizations, ASIC and FPGA codesign
National Category
Computer Engineering
Identifiers
URN: urn:nbn:se:liu:diva-16372ISBN: 978-91-7393-702-3 (print)OAI: oai:DiVA.org:liu-16372DiVA: diva2:158202
Public defence
2009-02-27, Visionen, Hus B, Campus Valla, Linköpings universitet, Linköping, 10:15 (English)
Opponent
Supervisors
Available from: 2009-02-02 Created: 2009-01-19 Last updated: 2015-02-18Bibliographically approved
List of papers
1. Using low precision floating point numbers to reduce memory cost for MP3 decoding
Open this publication in new window or tab >>Using low precision floating point numbers to reduce memory cost for MP3 decoding
2004 (English)In: International Workshop on Multimedia Signal Processing, IEEE Xplore , 2004, 119-122 p.Conference paper, Published paper (Refereed)
Abstract [en]

The purpose of our work has been to evaluate the practicality of using a 16-bit floating point representation to store the intermediate sample values and other data in memory during the decoding of MP3 bit streams. A floating point number representation offers a better trade-off between dynamic range and precision than a fixed point representation for a given word length. Using a floating point representation means that smaller memories can be used which leads to smaller chip area and lower power consumption without reducing sound quality. We have designed and implemented a DSP processor based on 16-bit floating point intermediate storage. The DSP processor is capable of decoding all MP3 bit streams at 20 MHz and this has been demonstrated on an FPGA prototype.

Place, publisher, year, edition, pages
IEEE Xplore, 2004
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-16559 (URN)10.1109/MMSP.2004.1436435 (DOI)0-7803-8578-0 (ISBN)
Available from: 2009-02-02 Created: 2009-02-02 Last updated: 2015-02-18Bibliographically approved
2. An FPGA based Open Source Network-on-chip Architecture
Open this publication in new window or tab >>An FPGA based Open Source Network-on-chip Architecture
2007 (English)In: 17th International Conference on Fileld Programmable Logic and Applications, FPL, Amsterdam, Holland, 2007, IEEE , 2007, 800-803 p.Conference paper, Published paper (Refereed)
Abstract [en]

Networks on chip (NoC) has long been seen as a potential solution to the problems encountered when implementing large digital hardware designs. In this paper we describe an open source FPGA based NoC architecture with low area overhead, high throughput and low latency compared to other published works. The architecture has been optimized for Xilinx FPGAs and the NoC is capable of operating at a frequency of 260 MHz in a Virtex-4 FPGA. We have also developed a bridge so that generic Wishbone bus compatible IP blocks can be connected to the NoC.

Place, publisher, year, edition, pages
IEEE, 2007
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-16560 (URN)10.1109/FPL.2007.4380772 (DOI)978-1-4244-1060-6 (ISBN)
Available from: 2009-02-02 Created: 2009-02-02 Last updated: 2015-02-18Bibliographically approved
3. Thinking outside the flow: Creating customized backend tools for Xilinx based designs
Open this publication in new window or tab >>Thinking outside the flow: Creating customized backend tools for Xilinx based designs
2007 (English)In: 4th annual FPGAworld Conference, Stockholm, 2007, 2007Conference paper, Published paper (Refereed)
Abstract [en]

This paper is intended to serve as an introduction to how to build a customized backend tool for a Xilinx based design flow. A Python based library called PyXDL is presented which allows a user to manipulate XDL files which contain a placed and routed design. Three different tools are presented which uses this library, ranging from a simple resource utilization viewer to a tool which will insert a logic analyzer into an already routed design, thus avoiding a costly complete rerun of the place and route tool.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-16561 (URN)
Available from: 2009-02-02 Created: 2009-02-02 Last updated: 2015-02-18Bibliographically approved
4. A High Performance Microprocessor with DSP Extensions Optimized for the Virtex-4 FPGA
Open this publication in new window or tab >>A High Performance Microprocessor with DSP Extensions Optimized for the Virtex-4 FPGA
2008 (English)In: International Conference on Field Programmable Logic and Applications FLP 2008, Heidelberg, Germany, 2008, 2008, 599-602 p.Conference paper, Published paper (Refereed)
Abstract [en]

As the use of FPGAs increases, the importance of highly optimized processors for FPGAs will increase. In this paper we present the microarchitecture of a soft microprocessor core optimized for the Virtex-4 architecture. The core can operate at 357 MHz, which is significantly faster than Xilinxpsila Microblaze architecture on the same FPGA. At this frequency it is necessary to keep the logic complexity down and this paper shows how this can be done while retaining sufficient functionality for a high performance processor.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-16562 (URN)10.1109/FPL.2008.4630018 (DOI)978-1-4244-1960-9 (ISBN)
Available from: 2009-02-02 Created: 2009-02-02 Last updated: 2015-02-18Bibliographically approved
5. High performance, low-latency field-programmable gate array-based floating-point adder and multiplier units in a Virtex 4
Open this publication in new window or tab >>High performance, low-latency field-programmable gate array-based floating-point adder and multiplier units in a Virtex 4
2008 (English)In: IET Computers and digital techniques, ISSN 1751-8601, Vol. 2, 305-313 p.Article in journal (Refereed) Published
Abstract [en]

There is increasing interest about floating-point arithmetics in field programmable gate arrays (FPGAs) because of the increase in their size and performance. FPGAs are generally good at bit manipulations and fixed-point arithmetics, but they have a harder time coping with floating-point arithmetics. An architecture used to construct high-performance floating-point components in a Virtex-4 FPGA is described in detail. Floating-point adder/subtracter and multiplier units have been constructed. The adder/subtracter can operate at a frequency of 377 MHz in a Virtex-4SX35 (speed grade -12).

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-16563 (URN)10.1049/iet-cdt:20070075 (DOI)
Available from: 2009-02-02 Created: 2009-02-02 Last updated: 2015-02-18Bibliographically approved
6. An ASIC Perspective on High Performance FPGA Design
Open this publication in new window or tab >>An ASIC Perspective on High Performance FPGA Design
2009 (English)Conference paper, Published paper (Refereed)
Abstract [en]

In this paper we discuss how various design components perform in both FPGAs and standard cell based ASICs. We also investigate how various common FPGA optimizations will effect the performance and area of an ASIC port. We find that most techniques that are used to optimize a design for an FPGA will not have a negative impact on the area in an ASIC. The intended audience for this paper are engineers charged with creating designs or IP cores that are optimized for both FPGAs and ASICs.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-16564 (URN)
Available from: 2009-02-02 Created: 2009-02-02 Last updated: 2015-02-18Bibliographically approved

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