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Complex-Multiplier Implementation for Resource Flexible Pipelined FFTs in FPGAs
Linköping University, Department of Electrical Engineering.
Linköping University, Department of Electrical Engineering.
2009 (English)Independent thesis Advanced level (degree of Master (Two Years)), 40 credits / 60 HE creditsStudent thesis
Abstract [en]

AbstractDifferent approaches for implementing a complex multiplier in pipelined FFT are considered andimplemented to find an efficient one in this project. The implemented design is synthesized on Cyclone IIand Stratix III to know the performance. The design is implemented with a focus of reducing the resourcesused. Some approaches resulted in the reduced number of DSP blocks and others resulted in reducednumber of LUTs. Analysis of Synthesis results is performed for different widths (bit lengths) of complexmultiplier approaches.

Place, publisher, year, edition, pages
2009. , 60 p.
Keyword
VHDL, FFT, FPGAs, complexmultiplier, LUT, DSP block, utilization and twiddle factors
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-16547ISRN: LITH-ISY-EX—09/4155—SEOAI: oai:DiVA.org:liu-16547DiVA: diva2:158209
Presentation
2009-01-27, Nollstället, B Building, Entrance 25, Electronics Systems, ISY, Linkoping, 10:00 (English)
Uppsok
teknik
Supervisors
Examiners
Available from: 2009-02-03 Created: 2009-01-30 Last updated: 2009-02-03Bibliographically approved

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CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf