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An FPGA based Open Source Network-on-chip Architecture
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.ORCID iD: 0000-0002-0111-2384
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
2007 (English)In: 17th International Conference on Fileld Programmable Logic and Applications, FPL, Amsterdam, Holland, 2007, IEEE , 2007, 800-803 p.Conference paper, Published paper (Refereed)
Abstract [en]

Networks on chip (NoC) has long been seen as a potential solution to the problems encountered when implementing large digital hardware designs. In this paper we describe an open source FPGA based NoC architecture with low area overhead, high throughput and low latency compared to other published works. The architecture has been optimized for Xilinx FPGAs and the NoC is capable of operating at a frequency of 260 MHz in a Virtex-4 FPGA. We have also developed a bridge so that generic Wishbone bus compatible IP blocks can be connected to the NoC.

Place, publisher, year, edition, pages
IEEE , 2007. 800-803 p.
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-16560DOI: 10.1109/FPL.2007.4380772ISBN: 978-1-4244-1060-6 (print)OAI: oai:DiVA.org:liu-16560DiVA: diva2:158391
Available from: 2009-02-02 Created: 2009-02-02 Last updated: 2015-02-18Bibliographically approved
In thesis
1. Performance driven FPGA design with an ASIC perspective
Open this publication in new window or tab >>Performance driven FPGA design with an ASIC perspective
2009 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

FPGA devices are an important component in many modern devices. This means that it is important that VLSI designers have a thorough knowledge of how to optimize designs for FPGAs. While the design flows for ASICs and FPGAs are similar, there are many differences as well due to the limitations inherent in FPGA devices. To be able to use an FPGA efficiently it is important to be aware of both the strengths and oweaknesses of FPGAs. If an FPGA design should be ported to an ASIC at a later stage it is also important to take this into account early in the design cycle so that the ASIC port will be efficient.

This thesis investigates how to optimize a design for an FPGA through a number of case studies of important SoC components. One of these case studies discusses high speed processors and the tradeoffs that are necessary when constructing very high speed processors in FPGAs. The processor has a maximum clock frequency of 357~MHz in a Xilinx Virtex-4 devices of the fastest speedgrade, which is significantly higher than Xilinx' own processor in the same FPGA.

Another case study investigates floating point datapaths and describes how a floating point adder and multiplier can be efficiently implemented in an FPGA.

The final case study investigates Network-on-Chip architectures and how these can be optimized for FPGAs. The main focus is on packet switched architectures, but a circuit switched architecture optimized for FPGAs is also investigated.

All of these case studies also contain information about potential pitfalls when porting designs optimized for an FPGA to an ASIC. The focus in this case is on systems where initial low volume production will be using FPGAs while still keeping the option open to port the design to an ASIC if the demand is high. This information will also be useful for designers who want to create IP cores that can be efficiently mapped to both FPGAs and ASICs.

Finally, a framework is also presented which allows for the creation of custom backend tools for the Xilinx design flow. The framework is already useful for some tasks, but the main reason for including it is to inspire researchers and developers to use this powerful ability in their own design tools.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2009. 165 p.
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1237
Keyword
FPGA Optimizations, ASIC and FPGA codesign
National Category
Computer Engineering
Identifiers
urn:nbn:se:liu:diva-16372 (URN)978-91-7393-702-3 (ISBN)
Public defence
2009-02-27, Visionen, Hus B, Campus Valla, Linköpings universitet, Linköping, 10:15 (English)
Opponent
Supervisors
Available from: 2009-02-02 Created: 2009-01-19 Last updated: 2015-02-18Bibliographically approved
2. Aspects of system-on-chip design for FPGAs
Open this publication in new window or tab >>Aspects of system-on-chip design for FPGAs
2008 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

Due to the increasing NRE costs of recent ASICs, the use of FPGAs is expected to continue to increase. While the first FPGAs were limited devices useful mainly for glue logic, todays FPGAs are highly capable devices used in many different application areas including telecommunication, multimedia, medical, and automotive. This means that many VLSI designers need to deal with FPGAs, either as the primary target, or as a prototype platform. The design methodology for an ASIC and FPGA are similar, but if high performance is expected from the FPGA, it is necessary to take FPGA limitations related to memories, data path components, I/O, and routing delays into account early in the design cycle for both FPGA prototyping and FPGA products.

This thesis investigates these limitations through three case studies of important VLSI building blocks. The thesis also discusses how a designer can gain additional information from the FPGA backend flow through custom tools and presents a framework for designing such tools.

The first case study discusses the opportunities and problems when designing both the data path and control path components of a high speed processor in an FPGA. The resulting processor core is a RISC processor with some DSP extensions which has a clock frequency which is significantly higher than the Micro blaze processor which has been specifically developed for Xilinx FPGAs. This case study focuses on the tradeoffs which are necessary to reach this performance in an FPGA.

The second case study describes how a floating point adder and multiplier can be optimized for FPGAs. This is a very important area as the use of floating point arithmetic can significantly reduce the design time of some applications. The solution presented in the thesis outperforms previous academic publications and has a performance similar to commercial offerings.

The third case study presents a packet switched Network-on-Chip (NoC) architecture. While NoCs are not commonly used in FPGA designs today it is expected that they will become an important component in future FPGA designs, especially when prototyping large NoC based ASICs.

Finally, a framework is presented which allows a designer to write custom backend tool by modifying Xilinx XDL files. While the framework is already useful for some tasks, the main reason for including it is to inspire both researchers and developers to look into this area by showing that it is actually quite easy to write such tools.

Place, publisher, year, edition, pages
Linköping: Linköpings universitet, 2008. 72 p.
Series
Linköping Studies in Science and Technology. Thesis, ISSN 0280-7971 ; 1376
Series
LiU-TEK-LIC, 45
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-42791 (URN)68799 (Local ID)978-91-7393-848-8 (ISBN)68799 (Archive number)68799 (OAI)
Presentation
2008-06-13, Sal Glashuset, Linköpings universitet, Linköping, 10:15 (Swedish)
Opponent
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2015-02-18

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