High performance, low-latency field-programmable gate array-based floating-point adder and multiplier units in a Virtex 4
2008 (English)In: IET Computers and digital techniques, ISSN 1751-8601, Vol. 2, 305-313 p.Article in journal (Refereed) Published
There is increasing interest about floating-point arithmetics in field programmable gate arrays (FPGAs) because of the increase in their size and performance. FPGAs are generally good at bit manipulations and fixed-point arithmetics, but they have a harder time coping with floating-point arithmetics. An architecture used to construct high-performance floating-point components in a Virtex-4 FPGA is described in detail. Floating-point adder/subtracter and multiplier units have been constructed. The adder/subtracter can operate at a frequency of 377 MHz in a Virtex-4SX35 (speed grade -12).
Place, publisher, year, edition, pages
2008. Vol. 2, 305-313 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-16563DOI: 10.1049/iet-cdt:20070075OAI: oai:DiVA.org:liu-16563DiVA: diva2:158401