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An ASIC Perspective on High Performance FPGA Design
Linköping University, Department of Electrical Engineering.ORCID iD: 0000-0002-0111-2384
Linköping University, Department of Electrical Engineering.
2009 (English)Conference paper (Refereed)
Abstract [en]

In this paper we discuss how various design components perform in both FPGAs and standard cell based ASICs. We also investigate how various common FPGA optimizations will effect the performance and area of an ASIC port. We find that most techniques that are used to optimize a design for an FPGA will not have a negative impact on the area in an ASIC. The intended audience for this paper are engineers charged with creating designs or IP cores that are optimized for both FPGAs and ASICs.

Place, publisher, year, edition, pages
National Category
Engineering and Technology
URN: urn:nbn:se:liu:diva-16564OAI: diva2:158403
Available from: 2009-02-02 Created: 2009-02-02 Last updated: 2015-02-18Bibliographically approved
In thesis
1. Performance driven FPGA design with an ASIC perspective
Open this publication in new window or tab >>Performance driven FPGA design with an ASIC perspective
2009 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

FPGA devices are an important component in many modern devices. This means that it is important that VLSI designers have a thorough knowledge of how to optimize designs for FPGAs. While the design flows for ASICs and FPGAs are similar, there are many differences as well due to the limitations inherent in FPGA devices. To be able to use an FPGA efficiently it is important to be aware of both the strengths and oweaknesses of FPGAs. If an FPGA design should be ported to an ASIC at a later stage it is also important to take this into account early in the design cycle so that the ASIC port will be efficient.

This thesis investigates how to optimize a design for an FPGA through a number of case studies of important SoC components. One of these case studies discusses high speed processors and the tradeoffs that are necessary when constructing very high speed processors in FPGAs. The processor has a maximum clock frequency of 357~MHz in a Xilinx Virtex-4 devices of the fastest speedgrade, which is significantly higher than Xilinx' own processor in the same FPGA.

Another case study investigates floating point datapaths and describes how a floating point adder and multiplier can be efficiently implemented in an FPGA.

The final case study investigates Network-on-Chip architectures and how these can be optimized for FPGAs. The main focus is on packet switched architectures, but a circuit switched architecture optimized for FPGAs is also investigated.

All of these case studies also contain information about potential pitfalls when porting designs optimized for an FPGA to an ASIC. The focus in this case is on systems where initial low volume production will be using FPGAs while still keeping the option open to port the design to an ASIC if the demand is high. This information will also be useful for designers who want to create IP cores that can be efficiently mapped to both FPGAs and ASICs.

Finally, a framework is also presented which allows for the creation of custom backend tools for the Xilinx design flow. The framework is already useful for some tasks, but the main reason for including it is to inspire researchers and developers to use this powerful ability in their own design tools.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2009. 165 p.
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1237
FPGA Optimizations, ASIC and FPGA codesign
National Category
Computer Engineering
urn:nbn:se:liu:diva-16372 (URN)978-91-7393-702-3 (ISBN)
Public defence
2009-02-27, Visionen, Hus B, Campus Valla, Linköpings universitet, Linköping, 10:15 (English)
Available from: 2009-02-02 Created: 2009-01-19 Last updated: 2015-02-18Bibliographically approved

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