This paper presents a pipeline analog-to-digital converter achieving 7.7 ENOB at 1.0 GS/s. A single-stage inverter-based amplifier is used with asymmetrical biasing of the pMOS and nMOS transistors and digitally controlled binary-weighted assisted capacitor chain for calibration in the gain stage. It results in an increased closed-loop linearity and a THD of-53.1 dB while allowing symmetrical layout, transconductances, and parasitic effects. With the amplifier in a switched-capacitor configuration, the optimal bias point can be maintained throughout the input range, which minimizes the power overhead of the MDAC. Calibration of the stage gain is digitally controlled through binary-weighted capacitor chain at gate of transistors which makes the power consumption of gain stage correction be avoided in digital domain. With a core power dissipation of 47.5 mW and an FoM of 0.355 pJ/conv-step, high sample rate is achieved in a medium resolution pipeline ADC without compromising the energy efficiency. © 2020 IEEE.