During the development of a real-time system the main goal is to find an implementation that satisfies the specified timing constraints. Often, it is most cost-effective to use a heterogeneous solution based on a mixture of different microprocessors and application-specific integrated circuits. There is however a lack of techniques to handle the development of heterogeneously implemented systems, and this thesis therefore presents a novel approach inspired by research in the area of hardware/software codesign. The behaviour of the entire system is specified in a high-level, homogeneous description, independently of how different parts will later be implemented, and a thorough design space exploration is performed at the system level using automatic or semi-automatic synthesis tools which operate on virtual prototypes of the implementation.

The objective of the synthesis is to find the least costly implementation which meets all timing constraints, and in order to predict these characteristics of the final system, different analysis methods are needed. The thesis presents an intrinsic analysis which estimates the hardware resource usage of individual tasks, and an extrinsic analysis for determining the effects of resource sharing between several concurrent tasks. The latter is similar to the fixed-priority schedulability analysis used for single-processor systems, but extended to heterogeneous architectures. Since these analysis procedures are applied early in the design process, there are always some discrepancies between the estimated data and the actual characteristics of the final system, and constructive ways of dealing with these inaccuracies are therefore also presented.

Several synthesis algorithms are proposed for different aspects of the design. The hardware architecture is assembled from a component library using heuristic search techniques, and three alternative algorithms are evaluated in the thesis. The optimal partitioning of the functionality on an architecture is found using a branch-and-bound algorithm. Finally, a fixed-priority scheduler is instantiated by assigning priorities to the concurrent tasks of the behaviour. Together, the proposed analysis and synthesis methods provide a solid basis for systematic engineering of heterogeneous real-time systems.