In many telecommunications applications, as mobile radio and internet access, analog filters and data converters are needed. The data converters are crucial building blocks that strongly influence the performance and price of the whole system. The traditional view on AID converters (ADCs) as numerical conversion devices does not always apply in telecommunications applications. Good dynamic performance is required. The objective of the work in this thesis is to find suitable ADC architectures and circuit techniques for telecommunications applications. We are mainly concerned with low-voltage circuits implemented in a CMOS process.

This thesis outlines the dynamic performance requirements on ADCs in telecommunications and presents tutorial discussions on most existing highspeed ADC architectures with emphasis on the dynamic performance at high signal frequencies. Based on these discussions we conclude that pipelined converters are good candidates since. they, contrary to oversampling and flash converters, can provide a high resolution over a large signal bandwidth.

To further increase the speed of the converter, time-interleaving can be used. However, mismatch in this type of converter will limit the dynamic performance. For high signal frequencies timing errors in the clock signals limits the performance. The timing problems can be solved by using a S/H circuit at the input of the time-interleaved converter. This S/H circuit may have a large power consumption and is difficult to design since it must be operated at a high speed. Therefore we propose a passive sampling technique that can reduce the effect of timing errors without increasing the power consumption.

There are in principle two circuit techniques available for implementation of pipelined converters, the Switched-Current (SI) technique and the Switched Capacitor(SC) technique. The limitations of the two techniques and how they affect the performance of pipelined converters are discussed. A novel SI architecture for pipelined converters is proposed and compared to existing architectures. The operational amplifier (op-amp) is a crucial part of any SCcircuit. In the thesis we consider frequency compensation of a low-voltage high-gain op-amp intended for SC pipelined ADCs. Several techniques are investigated and a nested compensation is shown to be a good choice.

A number of implementations have been made and are presented in the thesis. Based on the novel SI architecture, implementations were made in a standard digital CMOS process including a 2.5 V 20 MS/s 8-bit ADC and a 2.7 V analog interface for DECT. The passive sampling technique and the low-voltage op-amp mentioned above were used in a 2.5 V 40 MS/s 4-channe ltime-interleaved converter.

For moderate bandwidth requirements the Sigma-Delta converter may be an alternative to pipelined converters. In the thesis we present an implementation of a 4th order 5 V Sigma-Delta modulator. In addition to ADCs, we also present a technique for utilizing a voltage-to-current converter as a lowpass filter for low-cost current-mode oversampling data converters. A chip was fabricated using a 3.3 V supply voltage.