A synthesizable verilog model of serial protocol engine for USB 1.1 device
Independent thesis Advanced level (degree of Magister), 20 points / 30 hpStudent thesis
USB has become a popular interface for exchanging data between PC’s and peripherals. An increasing number of portable peripherals are using the USB interface to communicate with the PC.The design and implementation of a synthesizable model of the USB 1.1 protocol engine is presented in this report The PHY is compatible with the USB 1.1 transceiver macrocell interface (UTMI) specification and the simulation test confirmed the successful operation of circuits for both full speed (12 Mbps) and low speed (1.5 Mbps) data transmission. the model is written completely in behavioral verilog with a top down approach and the model was verified and validated.
Place, publisher, year, edition, pages
2007. , 71 p.
USB, exchaning data, PC, portable peripherials, PHY, UTMI, data transmission
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-10182ISRN: LiTH-ISY-EX--07/3977--SEOAI: oai:DiVA.org:liu-10182DiVA: diva2:16934
2007-06-11, notställ, B, Linkoping University, Linkoping, 08:00