Design of a High-Speed CMOS Comparator
Independent thesis Advanced level (degree of Magister), 20 points / 30 hpStudent thesis
This master thesis describes the design of high-speed latched comparator with 6-bit resolution, full scale voltage of 1.6 V and the sampling frequency of 250 MHz. The comparator is designed in a 0.35 9m CMOS process with a supply voltage of 3.3 V.
The comparator is designed for time-interleaved bandpass sigma-delta ADC.
Due to the nature of the target application, it should be possible to turn off the components to avoid the static power consumption. The comparator of this design implements the turn off technique when it is not in use. The settling time of the comparator is less than half the clock cycle which means it does not effect the functionality of the bandpass sigma-delta ADC in terms of speed.
The simulation results are derived using Cadence environment. The results show that the comparator has 6-bit resolution and power consumption of 4.13 mW for the worst-case frequency of 250 MHz. It fulfills all the performance requirements, most of them with large margins.
Place, publisher, year, edition, pages
Institutionen för systemteknik , 2007. , 30 p.
Comparator, CMOS comparator, Sigma-delta ADC, Low power design, High-speed.
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-10446ISRN: LiTH-ISY-EX--07/4121--SEOAI: oai:DiVA.org:liu-10446DiVA: diva2:17183
2007-11-07, Nollstället, D-korridor, Linkoping University, Linkoping, 15:15