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Design and implementation of a decimation filter using a multi-precision multiply and accumulate unit for an audio range delta sigma analog to digital converter
Linköping University, Department of Electrical Engineering.
2008 (English)Independent thesis Advanced level (professional degree), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

This work presents the design and implementation of a decimation filter for a three bits sigma delta analog to digital converter. The input is audio with a oversampling ratio of 32. Filter optimization and tradeoffs concerning the design is described. The filter is a multistage filter consisting of two cascaded FIR filters. The arithmetic unit is a multi-precision unit that can handle three or 24 bits MAC operations. The designed decimation filter is synthesized on standard cells of a 0.13 μm CMOS library.

Place, publisher, year, edition, pages
Institutionen för systemteknik , 2008. , 51 p.
Keyword [en]
decimation, digital filter, FIR, hardware implementation, multi precision, delta sigma
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-11261ISRN: LiTH-ISY-EX--08/4075--SEOAI: oai:DiVA.org:liu-11261DiVA: diva2:17668
Presentation
2008-02-22, Nollstället, B, Linköpings universitet, 581 83 LINKÖPING, 13:15 (English)
Uppsok
teknik
Supervisors
Examiners
Available from: 2008-04-03 Created: 2008-04-03Bibliographically approved

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CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf