Design and implementation of a decimation filter using a multi-precision multiply and accumulate unit for an audio range delta sigma analog to digital converter
Independent thesis Advanced level (professional degree), 20 credits / 30 HE creditsStudent thesis
This work presents the design and implementation of a decimation filter for a three bits sigma delta analog to digital converter. The input is audio with a oversampling ratio of 32. Filter optimization and tradeoffs concerning the design is described. The filter is a multistage filter consisting of two cascaded FIR filters. The arithmetic unit is a multi-precision unit that can handle three or 24 bits MAC operations. The designed decimation filter is synthesized on standard cells of a 0.13 μm CMOS library.
Place, publisher, year, edition, pages
Institutionen för systemteknik , 2008. , 51 p.
decimation, digital filter, FIR, hardware implementation, multi precision, delta sigma
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-11261ISRN: LiTH-ISY-EX--08/4075--SEOAI: oai:DiVA.org:liu-11261DiVA: diva2:17668
2008-02-22, Nollstället, B, Linköpings universitet, 581 83 LINKÖPING, 13:15 (English)