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A 5 GHz floating point multiply-accumulator in 90 nm dual VT CMOS
Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
Microprocessor Research Labs, Intel, Hillsboro, OR, USA.
Microprocessor Research Labs, Intel, Hillsboro, OR, USA.
Microprocessor Research Labs, Intel, Hillsboro, OR, USA.
Show others and affiliations
2003 (English)In: IEEE International Solid-State Circuits Conference, Digest of Technical Papers, IEEE , 2003, Vol. 1, 334-335 p.Conference paper, Published paper (Refereed)
Abstract [en]

A 32 b single-cycle floating point accumulator that uses base 32 and carry-save format with delayed addition is described. Combined algorithmic, logic and circuit techniques enable multiply-accumulate operation at 5 GHz. In a 90 nm 7M dual-VT CMOS process, the 2 mm2 prototype contains 230K transistors and dissipates 1.2 W at 5 GHz, 1.2 V and 25°C.

Place, publisher, year, edition, pages
IEEE , 2003. Vol. 1, 334-335 p.
Series
Digest of Technical Papers, ISSN 0193-6530 ; Vol. 1
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-13109DOI: 10.1109/ISSCC.2003.1234322ISBN: 0-7803-7707-9 (print)OAI: oai:DiVA.org:liu-13109DiVA: diva2:17853
Conference
2003 IEEE International Solid-State Circuits Conference, Digest of Technical Papers. ISSCC
Available from: 2008-04-01 Created: 2008-04-01 Last updated: 2011-03-02Bibliographically approved
In thesis
1. Performance and Energy Efficient Network-on-Chip Architectures
Open this publication in new window or tab >>Performance and Energy Efficient Network-on-Chip Architectures
2007 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The scaling of MOS transistors into the nanometer regime opens the possibility for creating large Network-on-Chip (NoC) architectures containing hundreds of integrated processing elements with on-chip communication. NoC architectures, with structured on-chip networks are emerging as a scalable and modular solution to global communications within large systems-on-chip. NoCs mitigate the emerging wire-delay problem and addresses the need for substantial interconnect bandwidth by replacing today’s shared buses with packet-switched router networks. With on-chip communication consuming a significant portion of the chip power and area budgets, there is a compelling need for compact, low power routers. While applications dictate the choice of the compute core, the advent of multimedia applications, such as three-dimensional (3D) graphics and signal processing, places stronger demands for self-contained, low-latency floating-point processors with increased throughput. This work demonstrates that a computational fabric built using optimized building blocks can provide high levels of performance in an energy efficient manner. The thesis details an integrated 80- Tile NoC architecture implemented in a 65-nm process technology. The prototype is designed to deliver over 1.0TFLOPS of performance while dissipating less than 100W.

This thesis first presents a six-port four-lane 57 GB/s non-blocking router core based on wormhole switching. The router features double-pumped crossbar channels and destinationaware channel drivers that dynamically configure based on the current packet destination. This enables 45% reduction in crossbar channel area, 23% overall router area, up to 3.8X reduction in peak channel power, and 7.2% improvement in average channel power. In a 150-nm sixmetal CMOS process, the 12.2 mm2 router contains 1.9-million transistors and operates at 1 GHz at 1.2 V supply.

We next describe a new pipelined single-precision floating-point multiply accumulator core (FPMAC) featuring a single-cycle accumulation loop using base 32 and internal carry-save arithmetic, with delayed addition techniques. A combination of algorithmic, logic and circuit techniques enable multiply-accumulate operations at speeds exceeding 3GHz, with singlecycle throughput. This approach reduces the latency of dependent FPMAC instructions and enables a sustained multiply-add result (2FLOPS) every cycle. The optimizations allow removal of the costly normalization step from the critical accumulation loop and conditionally powered down using dynamic sleep transistors on long accumulate operations, saving active and leakage power. In a 90-nm seven-metal dual-VT CMOS process, the 2 mm2 custom design contains 230-K transistors. Silicon achieves 6.2-GFLOPS of performance while dissipating 1.2 W at 3.1 GHz, 1.3 V supply.

We finally present the industry's first single-chip programmable teraFLOPS processor. The NoC architecture contains 80 tiles arranged as an 8×10 2D array of floating-point cores and packet-switched routers, both designed to operate at 4 GHz. Each tile has two pipelined singleprecision FPMAC units which feature a single-cycle accumulation loop for high throughput. The five-port router combines 100 GB/s of raw bandwidth with low fall-through latency under 1ns. The on-chip 2D mesh network provides a bisection bandwidth of 2 Tera-bits/s. The 15-FO4 design employs mesochronous clocking, fine-grained clock gating, dynamic sleep transistors, and body-bias techniques. In a 65-nm eight-metal CMOS process, the 275 mm2 custom design contains 100-M transistors. The fully functional first silicon achieves over 1.0TFLOPS of performance on a range of benchmarks while dissipating 97 W at 4.27 GHz and 1.07-V supply.

It is clear that realization of successful NoC designs require well balanced decisions at all levels: architecture, logic, circuit and physical design. Our results demonstrate that the NoC architecture successfully delivers on its promise of greater integration, high performance, good scalability and high energy efficiency.

Place, publisher, year, edition, pages
Institutionen för systemteknik, 2007. 93 p.
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1130
Keyword
Chips, MOS transistors, Network-on-Chip (NoC), process technology, FPMAC
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-11439 (URN)978-91-85895-91-5 (ISBN)
Public defence
2007-10-30, Visionen, Hus B, Campus US, Linköpings universitet, Linköping, 10:15 (English)
Opponent
Supervisors
Available from: 2008-04-01 Created: 2008-04-01 Last updated: 2009-05-18
2. Performance and Energy Efficient Building Blocks for Network-on-Chip Architectures
Open this publication in new window or tab >>Performance and Energy Efficient Building Blocks for Network-on-Chip Architectures
2006 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

The ever shrinking size of the MOS transistors brings the promise of scalable Network-on-Chip (NoC) architectures containing hundreds of processing elements with on-chip communication, all integrated into a single die. Such a computational fabric will provide high levels of performance in an energy efficient manner. To mitigate emerging wire-delay problem and to address the need for substantial interconnect bandwidth, packet switched routers are fast replacing shared buses and dedicated wires as the interconnect fabric of choice. With on-chip communication consuming a significant portion of the chip power and area budgets, there is a compelling need for compact, low power routers. While applications dictate the choice of the compute core, the advent of multimedia applications, such as 3D graphics and signal processing, places stronger demands for self-contained, low-latency floating-point processors with increased throughput. Therefore, this work focuses on two key building blocks critical to the success of NoC design: high performance, area and energy efficient router and floating-point processor architectures.

This thesis first presents a six-port four-lane 57 GB/s non-blocking router core based on wormhole switching. The router features double-pumped crossbar channels and destinationaware channel drivers that dynamically configure based on the current packet destination. This enables 45% reduction in crossbar channel area, 23% overall router area, up to 3.8X reduction in peak channel power, and 7.2% improvement in average channel power, with no performance penalty over a published design. In a 150nm six-metal CMOS process, the 12.2mm2 router contains 1.9 million transistors and operates at 1GHz at 1.2V. We next present a new pipelined single-precision floating-point multiply accumulator core (FPMAC) featuring a single-cycle accumulate loop using base 32 and internal carry-save arithmetic, with delayed addition techniques. Combined algorithmic, logic and circuit techniques enable multiply-accumulates at speeds exceeding 3GHz, with single-cycle throughput. Unlike existing FPMAC architectures, the design eliminates scheduling restrictions between consecutive FPMAC instructions. The optimizations allow removal of the costly normalization step from the critical accumulate loop and conditionally powered down using dynamic sleep transistors on long accumulate operations, saving active and leakage power. In addition, an improved leading zero anticipator (LZA) and overflow detection logic applicable to carry-save format is presented. In a 90nm seven-metal dual-VT CMOS process, the 2mm2 custom design contains 230K transistors. The fully functional first silicon achieves 6.2 GFLOPS of performance while dissipating 1.2W at 3.1GHz, 1.3V supply.

It is clear that realization of successful NoC designs require well balanced decisions at all levels: architecture, logic, circuit and physical design. Our results from key building blocks demonstrate the feasibility of pushing the performance limits of compute cores and communication routers, while keeping active and leakage power, and area under control.

Place, publisher, year, edition, pages
Institutionen för systemteknik, 2006. 51 p.
Series
Linköping Studies in Science and Technology. Thesis, ISSN 0280-7971 ; 1255
Series
Keyword
Network-on-Chip Architectures, floating-point units, tiled-architectures, crossbar routers, multi-processor interconnection
National Category
Computer Engineering
Identifiers
urn:nbn:se:liu:diva-7845 (URN)91-85523-54-2 (ISBN)
Presentation
2006-05-30, Glashuset, Campus Valla, Linköpings universitet, Linköping, 13:15 (English)
Opponent
Supervisors
Note
Report code: LiU-TEK-LIC-2006:36.Available from: 2007-01-31 Created: 2007-01-31 Last updated: 2009-06-08

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Citation style
  • apa
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  • modern-language-association-8th-edition
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  • Other style
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