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A 5.1GHz 0.34mm2 Router for Network-on-Chip Applications
Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
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2007 (English)In: 2007 IEEE Symposium on VLSI Circuits, IEEE , 2007, 42-43 p.Conference paper (Refereed)
Abstract [en]

A five-port two-lane pipelined packet-switched router core with phase-tolerant mesochronous links forms the key communication fabric for an 80-tile network-on-chip (NoC) architecture. The 15FO4 design combines 102 GB/s of raw bandwidth with low fall-through latency of 980 ps. A shared crossbar architecture with a double-pumped crossbar switch enables a compact 0.34 mm2 router layout. In a 65nm eight-metal CMOS process, the router contains 210K transistors and operates at 5.1GHz at 1.2 V, while dissipating 945 mW.

Place, publisher, year, edition, pages
IEEE , 2007. 42-43 p.
National Category
Engineering and Technology
URN: urn:nbn:se:liu:diva-13112DOI: 10.1109/VLSIC.2007.4342758ISBN: 978-4-900784-04-8ISBN: 978-4-900784-05-5OAI: diva2:17856
20th Symposium on VLSI Circuits
Available from: 2008-04-01 Created: 2008-04-01 Last updated: 2013-09-10
In thesis
1. Performance and Energy Efficient Network-on-Chip Architectures
Open this publication in new window or tab >>Performance and Energy Efficient Network-on-Chip Architectures
2007 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The scaling of MOS transistors into the nanometer regime opens the possibility for creating large Network-on-Chip (NoC) architectures containing hundreds of integrated processing elements with on-chip communication. NoC architectures, with structured on-chip networks are emerging as a scalable and modular solution to global communications within large systems-on-chip. NoCs mitigate the emerging wire-delay problem and addresses the need for substantial interconnect bandwidth by replacing today’s shared buses with packet-switched router networks. With on-chip communication consuming a significant portion of the chip power and area budgets, there is a compelling need for compact, low power routers. While applications dictate the choice of the compute core, the advent of multimedia applications, such as three-dimensional (3D) graphics and signal processing, places stronger demands for self-contained, low-latency floating-point processors with increased throughput. This work demonstrates that a computational fabric built using optimized building blocks can provide high levels of performance in an energy efficient manner. The thesis details an integrated 80- Tile NoC architecture implemented in a 65-nm process technology. The prototype is designed to deliver over 1.0TFLOPS of performance while dissipating less than 100W.

This thesis first presents a six-port four-lane 57 GB/s non-blocking router core based on wormhole switching. The router features double-pumped crossbar channels and destinationaware channel drivers that dynamically configure based on the current packet destination. This enables 45% reduction in crossbar channel area, 23% overall router area, up to 3.8X reduction in peak channel power, and 7.2% improvement in average channel power. In a 150-nm sixmetal CMOS process, the 12.2 mm2 router contains 1.9-million transistors and operates at 1 GHz at 1.2 V supply.

We next describe a new pipelined single-precision floating-point multiply accumulator core (FPMAC) featuring a single-cycle accumulation loop using base 32 and internal carry-save arithmetic, with delayed addition techniques. A combination of algorithmic, logic and circuit techniques enable multiply-accumulate operations at speeds exceeding 3GHz, with singlecycle throughput. This approach reduces the latency of dependent FPMAC instructions and enables a sustained multiply-add result (2FLOPS) every cycle. The optimizations allow removal of the costly normalization step from the critical accumulation loop and conditionally powered down using dynamic sleep transistors on long accumulate operations, saving active and leakage power. In a 90-nm seven-metal dual-VT CMOS process, the 2 mm2 custom design contains 230-K transistors. Silicon achieves 6.2-GFLOPS of performance while dissipating 1.2 W at 3.1 GHz, 1.3 V supply.

We finally present the industry's first single-chip programmable teraFLOPS processor. The NoC architecture contains 80 tiles arranged as an 8×10 2D array of floating-point cores and packet-switched routers, both designed to operate at 4 GHz. Each tile has two pipelined singleprecision FPMAC units which feature a single-cycle accumulation loop for high throughput. The five-port router combines 100 GB/s of raw bandwidth with low fall-through latency under 1ns. The on-chip 2D mesh network provides a bisection bandwidth of 2 Tera-bits/s. The 15-FO4 design employs mesochronous clocking, fine-grained clock gating, dynamic sleep transistors, and body-bias techniques. In a 65-nm eight-metal CMOS process, the 275 mm2 custom design contains 100-M transistors. The fully functional first silicon achieves over 1.0TFLOPS of performance on a range of benchmarks while dissipating 97 W at 4.27 GHz and 1.07-V supply.

It is clear that realization of successful NoC designs require well balanced decisions at all levels: architecture, logic, circuit and physical design. Our results demonstrate that the NoC architecture successfully delivers on its promise of greater integration, high performance, good scalability and high energy efficiency.

Place, publisher, year, edition, pages
Institutionen för systemteknik, 2007. 93 p.
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1130
Chips, MOS transistors, Network-on-Chip (NoC), process technology, FPMAC
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
urn:nbn:se:liu:diva-11439 (URN)978-91-85895-91-5 (ISBN)
Public defence
2007-10-30, Visionen, Hus B, Campus US, Linköpings universitet, Linköping, 10:15 (English)
Available from: 2008-04-01 Created: 2008-04-01 Last updated: 2009-05-18

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