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Shared Memory Access Pattern Analysis using Virtual Platforms
Linköping University, Department of Electrical Engineering.
2023 (English)Independent thesis Advanced level (degree of Master (Two Years)), 28 HE creditsStudent thesisAlternative title
Analys av åtkomster till delat minne med hjälp av en virtuell platform (Swedish)
Abstract [en]

Too keep up with System on Chip (SoC) solutions which are getting more compli- cated and increasing in scale, there is a need for the co-creation of software and hardware. Software-implemented hardware simulators, referred to as virtual platforms, are essential in the co-development of hardware and software. Early development, testing, and func- tional verification of the embedded SW are supported by a virtual platform. Ericsson uses virtual platforms to simulate Ericsson’s hardware which consists of several processors that run software that accesses data and instructions from a shared memory.

The thesis studies methods to analyze shared memory accesses to allow software de- velopers to make the utilization of the memory accesses more efficient. A set of scripts were developed which together creates a tool for SW developers at Ericsson to study how the Virtual platform utilizes the shared memory. The tool allows to read and process log files produced from the virtual platform, which is then used to determine the quality of the address accesses, read/write operations, and semaphore usage. The address usage is ana- lyzed by using an algorithm, referred to as access bundling, which detects several accesses of the same operation within a short time frame and address range. The read/write oper- ation quality is analyzed by utilizing histograms to visualize the most common number of bytes that were read and written, since generally large read/write operations are preferred over several small bytes read/written. A dynamic time warping algorithm was also im- plemented to determine whether the read/write operations for threads follow an optimal pattern of having large accesses at the start and end of a thread run with smaller accesses in between. The dynamic time warping algorithm produces a score for each thread run de- pending on how well it fits to this desired pattern. The semaphore usage is studied using an algorithm that detects if there are any blocks caused by two or more wait or signal op- erators in a row. The number of semaphores blocked is then visualized using scatter plots and tables.

Additionally, K-means, local outlier factor, and isolation forest was used as a way to detect anomalies regarding shared memory accesses. The algorithms determined whether a certain thread consists of an unusual number of accesses or a large average size of bytes read and written. The results from this did show that the algorithms gave a general overview of potential anomalies in shared memory access but further work needs to be done on this aspect for it to be useful for software developers, as no evaluation was done on the algorithms. This part of the work was used as a way to show that it is possible to implement machine learning algorithms to gain more insight into shared memory accesses.

Place, publisher, year, edition, pages
2023.
National Category
Computer Systems
Identifiers
URN: urn:nbn:se:liu:diva-199663OAI: oai:DiVA.org:liu-199663DiVA, id: diva2:1820138
Available from: 2023-12-18 Created: 2023-12-15 Last updated: 2023-12-18Bibliographically approved

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