Reduction of Simultaneous Switching Noise in Analog Signal Band on a Chip
Independent thesis Basic level (professional degree), 20 points / 30 hpStudent thesis
In the era of VLSI the technological advancements have lead us to integrate not only digital circuits of high device density but both digital and analog circuits on to the same chip. In recent years the number of devices on a chip has spectacularly increased, all
because of the downward scaling in sizes of the devices. But because of this dramatic scaling the devices have become more sensitive to the power-ground noise. Now in designing a mix signal system within single silicon die that has high speed digital circuits
along with high performance analog circuits the digital switching noise becomes a foremost concern for the correct functioning of the system.
The purpose of the thesis is to evaluate the reduction of Simultaneous Switching Noise in analog signal band with in the chip. The experiment is done by the use of DCVSL circuits combined with a novel method of implementation, instead of the common static circuits in the core design. These DCVSL circuits have the property to draw periodic currents from the power supply. So if the circuit draws equal amount of current at each clock cycle independent of the input fed to it, the generated noise’s frequency content, produced due to current spikes will then be shifted above the input clock frequency.
The idea is to reduce Simultaneous Switching Noise (SSN) by half of the clock frequency in the frequency band. This frequency band often contains to the analog signal band of a digital-to-analog converter. To evaluate the method two pipelined adders have been implemented in 0.13 μm CMOS technology. The proposed method (test circuit) is
implemented using DCVSL techniques and the reference circuit using static CMOS logic. For testing of the design we generated the input data on-chip. The pseudo-random data is generated by implementing two different length PRBS. We have also implemented a ROM containing specific test patterns. In the end, we have achieved a 10 dB decrease of noise level at the substrate node on the chip.
Place, publisher, year, edition, pages
Institutionen för systemteknik , 2008. , 120 p.
CMOS, DCVSL, PRBS, ROM, TSPCL, Implementation on Chip, Noise Reduction, Substrate noise, Simultaneously
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-12249ISRN: LiTH-ISY-EX--08/4187--SEOAI: oai:DiVA.org:liu-12249DiVA: diva2:18490
2008-06-03, Filterat, B house, Linköping University,Valla Campus, Linköping, 10:00