TIR, design and testing of a Simple GALS
Independent thesis Basic level (professional degree)Student thesis
Globally-asynchronous locally-synchronous (GALS) systems may become a solution for nowadays challenges in the field of VLSI design. Fully synchronous chips are becoming not feasible anymore due to clock distribution and power consumtion problems. The value of GALS lies in combination of well know synchronous design methods and relative simple asynchronous communication channels.
The key components are the communication control ports around the synchronous modules and the stretchable clock also called a wrapper. This clock has a unbound delay and is controlled by events the asynchronous channel.
A simple GALS system consisting of a 4-bit transmitter, integrator and receiver has been designed and layouted for a 0,35 micron CMOS proces. A 4-phase bundled protocol is used with GasP FIFO's. Novel circuits has been designed to switch from the one wire asynchronous communication of the FIFO to the 4-phase of the wrapper.
The report also dicusses the challenges for manufature test on asynchronous designs. A test strategy for GALS systems is been devoloped.
Place, publisher, year, edition, pages
Institutionen för systemteknik , 2002. , 32 p.
Electronics, GALS, asynchronous, design, testing
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-1258OAI: oai:DiVA.org:liu-1258DiVA: diva2:18575