Modelling of Power Dissipation in CMOS DACs
Independent thesis Basic level (professional degree)Student thesisAlternative title
Modellering av effektförbrukning i CMOS DA-omvandlare (Swedish)
In this master thesis work, the power dissipation in a current-steering digital- to-analog converter, DAC, has been studied. The digital as well as the analog power dissipation have been modelled in MATLAB and it is shown that the MATLAB models agrees well with simulation results from the circuit simulator (Spectre).
A case study on a DAC designed at Ericsson Microelectronics AB in Linköping has also been done. The DAC is a thermometer-coded current-steering DAC suitable for telecommunications applications. The telecommunication standards that have been studied are asymmetric digital subscriber line, ADSL, very high speed data digital subscriber line, VDSL, and, wireless local area network, WLAN. The conlusion of the study is that the power dissipation of the specific DAC, used in ADSL applications, 75mW, is far from optimized. It can theoretically be lowered to 3.5mW.
Place, publisher, year, edition, pages
Institutionen för systemteknik , 2002.
Electronics, DAC, power consumption, power dissipation, telecommunications
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-1329OAI: oai:DiVA.org:liu-1329DiVA: diva2:18651