Design of a Low Power, High Performance Track-and-Hold Circuit in a 0.18µm CMOS Technology
Independent thesis Basic level (professional degree)Student thesisAlternative title
Design av en lågeffekts högprestanda track-and-hold krets i en 0.18µm CMOS teknologi. (Swedish)
This master thesis describes the design of a track-and-hold (T&H) circuit with 10bit resolution, 80MS/s and 30MHz bandwidth. It is designed in a 0.18µm CMOS process with a supply voltage of 1.8 Volt. The circuit is supposed to work together with a 10bit pipelined analog to digital converter.
A switched capacitor topology is used for the T&H circuit and the amplifier is a folded cascode OTA with regulated cascode. The switches used are of transmission gate type.
The thesis presents the design decisions, design phase and the theory needed to understand the design decisions and the considerations in the design phase.
The results are based on circuit level SPICE simulations in Cadence with foundry provided BSIM3 transistor models. They show that the circuit has 10bit resolution and 7.6mW power consumption, for the worst-case frequency of 30MHz. The requirements on the dynamic performance are all fulfilled, most of them with large margins.
Place, publisher, year, edition, pages
Institutionen för systemteknik , 2002. , 84 p.
Electronics, track-and-hold, CMOS, 0.18, low power, high performance, 10-bit, folded cascode, switch theory, correlated double sampling, CDS, fully differential, gain boosting, regulated cascode, transmission gate, transmission gate switch, clock generator, clock driver, bias, bias circuit, amplifier design, switch design, common mode feedback, CMFB, 80MSPS, 80MS/s
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-1353OAI: oai:DiVA.org:liu-1353DiVA: diva2:18676