Feasibility study: Implementation of a gigabit Ethernet controller using an FPGA
Independent thesis Basic level (professional degree)Student thesis
Background: Many systems that Enea Epact AB develops for theirs customers communicates with computers. In order to meet the customers demands on cost effective solutions, Enea Epact wants to know if it is possible to implement a gigabit Ethernet controller in an FPGA. The controller shall be designed with the intent to meet the requirements of IEEE 802.3.
Aim: Find out if it is feasible to implement a gigabit Ethernet controller using an FPGA. In the meaning of feasible, certain constraints for size, speed and device must be met.
Method: Get an insight of the standard IEEE 802.3 and make a rough design of a gigabit Ethernet controller in order to identify parts in the standard that might cause problem when implemented in an FPGA. Implement the selected parts and evaluate the results.
Conclusion: It is possible to implement a gigabit Ethernet controller using an FPGA and the FPGA does not have to be a state-of-the-art device.
Place, publisher, year, edition, pages
Institutionen för systemteknik , 2003. , 88 p.
Datorteknik, CRC, Data Link Layer, Ethernet, FPGA, gigabit, GMII, MAC, MDI, MII, OSI/BR model, RS, PHY, Physical Layer
IdentifiersURN: urn:nbn:se:liu:diva-1681OAI: oai:DiVA.org:liu-1681DiVA: diva2:19005