Implementation of a Program Address Generator in a DSP processor
Independent thesis Basic level (professional degree)Student thesisAlternative title
Implementering av en Programadress generator i en DSP processor (Swedish)
The purpose of this thesis is to construct a"Program Address Generator"(PAG) to a 24-bit Harvard type, RISC DSP processor using the VHDL language. The PAG is a part of the program control unit, and should consist of the following units:
A system stack for storing jump and loop information. A program counter, a status register, a stack pointer, an operating mode register and two registers called loop address and loop counter register, to support hardware loops.
The PAG handles the fetch stage of the processor pipeline, and should handle instructions such as the jump, subroutine jump, return from subroutine/interrupt and loop instructions, among others.
The PAG was successfully designed, and its function verified through extensive tests, where common combinations of ASM instructions were tested. Files for automated testing was created, to support easy testing if only small changes are applied to the PAG.
Place, publisher, year, edition, pages
Institutionen för systemteknik , 2003. , 34 p.
Electronics, DSP, Program Control Unit, VHDL, fetch, pipeline, branch hazard, RISC, stack, program counter, status register
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-1742OAI: oai:DiVA.org:liu-1742DiVA: diva2:19068