This thesis investigates how systolic architectures can be used in the implementation of an arithmetic unit for small finite fields of characteristic two with polynomial basis representation.

Systolic architectures provide very high performance but also consume a lot of chip area. A number of design methods for tailoring the systolic arrays for a specified requirement are presented, making it possible to trade throughput, chip area and propagation delays for oneanother.

A study is also made on how these systolic arrays can be combined to form an arithmetic logic unit, ALU, that canperform operations in many different fields. A number of design alternatives are presented, and an example ALU is presented to give an idea of the performance of such a circuit.