Implementation of Pipelined Bit-parallel Adders
Independent thesis Basic level (professional degree)Student thesis
Bit-parallel addition can be performed using a number of adder structures with different area and latency. However, the power consumption of different adder structures is not well studied. Further, the effect of pipelining adders to increase the throughput is not well studied. In this thesis four different adders are described, implemented in VHDL and compared after synthesis. The results give a general idea of the time-delay-power tradeoffs between the adder structures. Pipelining is shown to be a good technique for increasing the circuit speed.
Place, publisher, year, edition, pages
Institutionen för systemteknik , 2003. , 52 p.
Electronics, Adder, Ripple carry adder, Carry look-ahead adder, Carry select adder, Carry save adder, Pipelining, Power consumption
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-1943OAI: oai:DiVA.org:liu-1943DiVA: diva2:19270