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Implementation of Pipelined Bit-parallel Adders
Linköping University, Department of Electrical Engineering.
2003 (English)Independent thesis Basic level (professional degree)Student thesis
Abstract [en]

Bit-parallel addition can be performed using a number of adder structures with different area and latency. However, the power consumption of different adder structures is not well studied. Further, the effect of pipelining adders to increase the throughput is not well studied. In this thesis four different adders are described, implemented in VHDL and compared after synthesis. The results give a general idea of the time-delay-power tradeoffs between the adder structures. Pipelining is shown to be a good technique for increasing the circuit speed.

Place, publisher, year, edition, pages
Institutionen för systemteknik , 2003. , 52 p.
Series
LiTH-ISY-Ex, 3459
Keyword [en]
Electronics, Adder, Ripple carry adder, Carry look-ahead adder, Carry select adder, Carry save adder, Pipelining, Power consumption
Keyword [sv]
Elektronik
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-1943OAI: oai:DiVA.org:liu-1943DiVA: diva2:19270
Uppsok
teknik
Available from: 2003-10-07 Created: 2003-10-07

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CiteExportLink to record
Permanent link

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Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf