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Behavioral model of an address generation unit
Linköping University, Department of Electrical Engineering.
2003 (English)Independent thesis Basic level (professional degree)Student thesisAlternative title
Beteendemodel för en adressgenereringsenhet (Swedish)
Abstract [en]

This thesis is a part of a bigger project which goal is to make a DSP that is instruction compatible with the Motorola DSP56002. The goal of this part is to make a behavioural model with timing of the address generation unit in the DSP.

The AGU unit can handle 4 different types of arithmetic’s including linear addressing, modulo addressing, wrap around modulo addressing and reverse carry addressing. It also handles several ways of calculating addresses as post/pre increment/decrement by a number. It can address 3 different memories, where 2 new addresses can be calculated at the same time in different memories.

This model will be used as a golden model for the RTL model of the AGU that is one of the main parts in the DSP.

Place, publisher, year, edition, pages
Institutionen för systemteknik , 2003.
Series
LiTH-ISY-Ex, 0271
Keyword [en]
Electronics, VHDL, DSP, AGU, adress generation unit, modulo
Keyword [sv]
Elektronik
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-2106OAI: oai:DiVA.org:liu-2106DiVA: diva2:19435
Uppsok
teknik
Available from: 2004-01-12 Created: 2004-01-12

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CiteExportLink to record
Permanent link

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Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf