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Performance Analysis and Implementation of Full Adder Cells Using 0.18 um CMOS Technology
Linköping University, Department of Electrical Engineering.
2003 (English)Independent thesis Basic level (professional degree)Student thesis
Abstract [en]

0.18 um CMOS technology is increasingly used in design and implementation of full adder cells. Hence, there is a need for better understanding of the effects of different cell designs on cell performance, including power dissipation and time delays.

This thesis contributes to better understanding of the behavior of single-bit full adder cells when low power-delay products are essential. Thirty one single-bit full adder cells have been implemented in Cadence tool suit and simulated using 0.18 µm CMOS technology to obtain a comprehensive study of the performance of the cells with respect to time (time-delays) and power consumption (power dissipation).

Simulation method used for performance measurements has been carefully devised to achieve as accurate measurements as possible with respect to time delay and power dissipation. The method combines the simple measurement technique for obtaining accurate time-delays and power dissipation of a cell, and the transistor resizing technique that allows systematicallyresizing of transistors to achieve minimal power-delay product. The original technique of sizing of the transistors has been extended in this thesis for the purpose of the performance measurements to include both resizing the transistors in the critical path and resizing the transistors on the global level, and therefore efficiently obtain minimal power-delay product for every cell.

The result of this performance study is an extensive knowledge of full adder cell behaviour with respect to time and power, including the limitations of the 0.18 µm CMOS technology when used in the area of full adder cells. Furthermore, the study identified full adder cell designs that demonstrated the best performance results with respect to power-delay products.

In general, the complex performance simulation method in this thesis that combines the simulation of time delay and critical path transistor resizing provides the most accurate measurements and as such can be used in the future performance analysis of single-bit full adder cells.

Place, publisher, year, edition, pages
Institutionen för systemteknik , 2003. , 78 p.
Series
LiTH-ISY-Ex-ET, 0266
Keyword [en]
Electronics, CMOS, full-adder cell, time-delay, power dissipation, performance
Keyword [sv]
Elektronik
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-2111OAI: oai:DiVA.org:liu-2111DiVA: diva2:19440
Uppsok
teknik
Available from: 2004-01-13 Created: 2004-01-13

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CiteExportLink to record
Permanent link

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Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
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  • asciidoc
  • rtf