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A New Mesochronous Clocking Scheme for Synchronization in System-on-Chip
Linköping University, Department of Electrical Engineering.
2004 (English)Independent thesis Basic level (professional degree)Student thesis
Abstract [en]

All large-scale digital Integrated Circuits need an appropriate strategy for clocking and synchronization. In large-scale and high-speed System-on-Chips (SoC), the traditional"Globally Synchronous"(GS) approach is not longer viable, due to severe wire delays. Instead new solutions as"Globally Synchronous, Locally Asynchronous"(GALS) approaches have been proposed. We propose to replace the GALS approach with a mesochronous clocking principle. In this work, such an approach together with a circuit solution in 0.18mm CMOS process has been presented. This solution allows clocking frequencies up to 4 GHz.

Place, publisher, year, edition, pages
Institutionen för systemteknik , 2004. , 42 p.
Series
LiTH-ISY-Ex, 3438
Keyword [en]
Electronics, Mesochronous, Metastability, Synchronization, Integrated Circuits
Keyword [sv]
Elektronik
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-2117OAI: oai:DiVA.org:liu-2117DiVA: diva2:19446
Uppsok
teknik
Available from: 2004-01-20 Created: 2004-01-20

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CiteExportLink to record
Permanent link

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Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf