A New Mesochronous Clocking Scheme for Synchronization in System-on-Chip
Independent thesis Basic level (professional degree)Student thesis
All large-scale digital Integrated Circuits need an appropriate strategy for clocking and synchronization. In large-scale and high-speed System-on-Chips (SoC), the traditional"Globally Synchronous"(GS) approach is not longer viable, due to severe wire delays. Instead new solutions as"Globally Synchronous, Locally Asynchronous"(GALS) approaches have been proposed. We propose to replace the GALS approach with a mesochronous clocking principle. In this work, such an approach together with a circuit solution in 0.18mm CMOS process has been presented. This solution allows clocking frequencies up to 4 GHz.
Place, publisher, year, edition, pages
Institutionen för systemteknik , 2004. , 42 p.
Electronics, Mesochronous, Metastability, Synchronization, Integrated Circuits
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-2117OAI: oai:DiVA.org:liu-2117DiVA: diva2:19446