Evaluation of Hardware Test Methods for VLSI Systems
Independent thesis Advanced level (degree of Magister), 10 points / 15 hpStudent thesis
The increasing complexity and decreasing technology feature sizes of electronic designs has caused the challenge of testing to grow over the last decades. The purpose of this thesis was to evaluate different hardware test methods/approaches based on their applicability in a complex SoC design. Among the aspects that were investigated are test implementation effort, test efficiency and the performance penalties implicated by the test.
This report starts out by presenting a general introduction to the basics of hardware testing. It then moves on to review available standards and methodologies. In the end one of the more interesting methods is investigated through a case study. The method that was chosen for the case study has been implemented on a DSP, and is rather new and not as prolific as many of the standards discussed in the report. This type of method appears to show promising results when compared to more traditional ones.
Place, publisher, year, edition, pages
Institutionen för systemteknik , 2005. , 60 p.
Electrical engineering, Hardware testing, Testability, JTAG, CTAG.
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-239ISRN: LiTH-ISY- EX-ET--05/0315--SEOAI: oai:DiVA.org:liu-239DiVA: diva2:19721