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Power Estimation of High Speed Bit-Parallel Adders
Linköping University, Department of Electrical Engineering.
2004 (English)Independent thesis Basic level (professional degree)Student thesisAlternative title
Effektestimering av snabba bitparallella adderare (Swedish)
Abstract [en]

Fast addition is essential in many DSP algorithms. Various structures have been introduced to speed up the time critical carry propagation. For high throughput applications, however, it may be necessary to introduce pipelining. In this report the power consumption of four different adder structures, with varying word length and different number of pipeline cuts, is compared.

Out of the four adder structures compared, the Kogge-Stone parallel prefix adder proves to be the best choice most of the time. The Brent-Kung parallel prefix adder is also a good choice, but the maximal throughput does not reach as high as the maximal throughput of the Kogge-Stone parallel prefix adder.

Place, publisher, year, edition, pages
Institutionen för systemteknik , 2004. , 79 p.
LiTH-ISY-Ex, 3534
Keyword [en]
Electronics, Power simulations, Pipelining, Adder, Ripple carry, Conditional sum, Brent-Kung, Kogge-Stone, Parallel prefix, VHDL, DSP
Keyword [sv]
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
URN: urn:nbn:se:liu:diva-2390OAI: diva2:19722
Available from: 2004-06-07 Created: 2004-06-07

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